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Bit size for R_AARCH64_*_ABS_LO12_NC relocations fixed

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Nicolas 2025-10-30 16:08:38 +01:00
parent d8e77d9572
commit 5ee63efeb7
1 changed files with 3 additions and 3 deletions
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6
src/pelfy/_fields_data.py
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@ -447,9 +447,9 @@ relocation_table_types = {
280: ("R_AARCH64_CONDBR19", 19, "S + A - P"), 280: ("R_AARCH64_CONDBR19", 19, "S + A - P"),
282: ("R_AARCH64_JUMP26", 26, "S + A - P"), 282: ("R_AARCH64_JUMP26", 26, "S + A - P"),
283: ("R_AARCH64_CALL26", 26, "S + A - P"), 283: ("R_AARCH64_CALL26", 26, "S + A - P"),
284: ("R_AARCH64_LDST16_ABS_LO12_NC", 16, "S + A"), 284: ("R_AARCH64_LDST16_ABS_LO12_NC", 12, "S + A"),
285: ("R_AARCH64_LDST32_ABS_LO12_NC", 32, "S + A"), 285: ("R_AARCH64_LDST32_ABS_LO12_NC", 12, "S + A"),
286: ("R_AARCH64_LDST64_ABS_LO12_NC", 64, "S + A"), 286: ("R_AARCH64_LDST64_ABS_LO12_NC", 12, "S + A"),
287: ("R_AARCH64_MOVW_PREL_G0", 16, "S + A - P"), 287: ("R_AARCH64_MOVW_PREL_G0", 16, "S + A - P"),
288: ("R_AARCH64_MOVW_PREL_G0_NC", 16, "S + A - P"), 288: ("R_AARCH64_MOVW_PREL_G0_NC", 16, "S + A - P"),
289: ("R_AARCH64_MOVW_PREL_G1", 32, "S + A - P"), 289: ("R_AARCH64_MOVW_PREL_G1", 32, "S + A - P"),