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@ -36,53 +36,5 @@ limitations under the License.
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#define S_READY_H 9
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#define S_READY_H 9
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#define S_ACTIVE_H 10
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#define S_ACTIVE_H 10
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void setupNfcEmulator(uint8_t *storage, uint16_t storageSize);
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void checkForNfcReader();/*****************************************************************************
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Written and Copyright (C) by Nicolas Kruse
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*****************************************************************************/
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//#define F_CPU 13560000UL
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//#define F_CPU 22000000UL
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//For ATiny*4:
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#define AIN1_PORT 2 //Port for OC0A on ATiny*4 is PA2
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#define AIN1_PRNG PORTA
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//For ATiny*5:
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//#define AIN1_PORT 1 //Port for OC0A on ATiny*5 is PB1
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//#define AIN1_PRNG PORTB
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#define RFID_FREQU 13560000UL
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#define CLC_PBIT (uint16_t)(128.0 * F_CPU / RFID_FREQU + 0.5)
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#define CMIN CLC_PBIT * 3 / 4
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#define CLCS CLC_PBIT * 5 / 4
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#define CLCM CLC_PBIT * 7 / 4
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#define CLCL CLC_PBIT * 9 / 4
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#define FDT_DELAY_BD9 (uint16_t)(9.0 * 128 * F_CPU / RFID_FREQU - 1) //Nr of cycles-1 for 9 bit durations
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#define FDT_DELAY_BIT0 (FDT_DELAY_BD9 + 20 - CLCL)
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#define FDT_DELAY_BIT1 (FDT_DELAY_BD9 + 84 - CLCL)
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#define SUBC_OVF (uint8_t)(F_CPU / 847500 / 2 - 1) //847500 Hz Subcarrier
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#define S_IDLE 0
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#define S_READY 1
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#define S_ACTIVE 2
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#define S_HALT 8
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#define S_READY_H 9
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#define S_ACTIVE_H 10
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void setupNfcEmulator(uint8_t *storage, uint16_t storageSize);
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void setupNfcEmulator(uint8_t *storage, uint16_t storageSize);
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void checkForNfcReader();
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void checkForNfcReader();
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