Some bugs fixed for the use with none 13.56 MHz crystals
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mail001@ntalk.de
parent
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commit
2b8fb8e0f7
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@ -1,396 +1,401 @@
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/*****************************************************************************
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/*****************************************************************************
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Written and Copyright (C) by Nicolas Kruse
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Written and Copyright (C) by Nicolas Kruse
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Licensed under the Apache License, Version 2.0 (the "License");
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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See the License for the specific language governing permissions and
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limitations under the License.
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limitations under the License.
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*****************************************************************************/
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*****************************************************************************/
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#include <avr/io.h>
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#include <avr/io.h>
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#include <util/delay.h>
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#include <util/delay.h>
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#include "nfcemulator.h"
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#include "nfcemulator.h"
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static uint8_t RX_MASK[18] = {0, 1, 0, 2, 0, 4, 0, 8, 0, 16, 0, 32, 0, 64, 0, 128, 0, 0};
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static uint8_t RX_MASK[18] = {0, 1, 0, 2, 0, 4, 0, 8, 0, 16, 0, 32, 0, 64, 0, 128, 0, 0};
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static uint8_t TX_MASK[8] = {1, 2, 4, 8, 16, 32, 64, 128};
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static uint8_t TX_MASK[8] = {1, 2, 4, 8, 16, 32, 64, 128};
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static uint16_t FDT_DELAY[2] = {FDT_DELAY_BIT0, FDT_DELAY_BIT1};
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static uint16_t FDT_DELAY[2] = {FDT_DELAY_BIT0, FDT_DELAY_BIT1};
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static uint8_t REQA[1] = {0x26};
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static uint8_t REQA[1] = {0x26};
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static uint8_t WUPA[1] = {0x52};
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static uint8_t WUPA[1] = {0x52};
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static uint8_t HLTA[4] = {0x50, 0x00, 0x57, 0}; //'50' '00' CRC_A
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static uint8_t HLTA[4] = {0x50, 0x00, 0x57, 0}; //'50' '00' CRC_A
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static uint8_t ATQA[2] = {0x44, 0x00}; //Anticollision with udi size = double
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static uint8_t ATQA[2] = {0x44, 0x00}; //Anticollision with udi size = double
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static uint8_t SEL_CL1[2] = {0x93, 0x20};
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static uint8_t SEL_CL1[2] = {0x93, 0x20};
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static uint8_t SEL_CL2[2] = {0x95, 0x20};
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static uint8_t SEL_CL2[2] = {0x95, 0x20};
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static uint8_t CT_UID1[5] = {0x88, 0x04, 0xE3, 0xEF, 0}; //uid0 uid1 uid2 uid3 BCC
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static uint8_t CT_UID1[5] = {0x88, 0x04, 0xE3, 0xEF, 0}; //uid0 uid1 uid2 uid3 BCC
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static uint8_t UID2[5] = {0xA2, 0xEF, 0x20, 0x80, 0}; //uid3 uid4 uid5 uid6 BCC
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static uint8_t UID2[5] = {0xA2, 0xEF, 0x20, 0x80, 0}; //uid3 uid4 uid5 uid6 BCC
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static uint8_t SAK_NC[3] = {0x04, 0xDA, 0x17}; //Select acknowledge uid not complete
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static uint8_t SAK_NC[3] = {0x04, 0xDA, 0x17}; //Select acknowledge uid not complete
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static uint8_t SAK_C[3] = {0x00, 0xFE, 0x51}; //Select acknowledge uid complete, Type 2 (PICC not compliant to ISO/IEC 14443-4)
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static uint8_t SAK_C[3] = {0x00, 0xFE, 0x51}; //Select acknowledge uid complete, Type 2 (PICC not compliant to ISO/IEC 14443-4)
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static uint8_t READ[1] = {0x30};
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static uint8_t READ[1] = {0x30};
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static uint8_t WRITE[1] = {0xA2};
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static uint8_t WRITE[1] = {0xA2};
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uint8_t *sto; //Pointer to tag content
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uint8_t *sto; //Pointer to tag content
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uint16_t stoSize; //Number of avalible bytes on the tag
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uint16_t stoSize; //Number of avalible bytes on the tag
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uint8_t buffer[64];
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uint8_t buffer[64];
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uint8_t rCount = 0;
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uint8_t rCount = 0;
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void setupNfcEmulator(uint8_t *storage, uint16_t storageSize)
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void setupNfcEmulator(uint8_t *storage, uint16_t storageSize)
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{
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{
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//clock divider for 8 bit timer0: clk/1 -> 13.5225 MHz
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//clock divider for 8 bit timer0: clk/1 -> 13.5225 MHz
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TCCR0B |= (1<<CS00);
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TCCR0B |= (1<<CS00);
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//8 bit timer0: Toggle OC0A on Compare Match and CTC-Mode
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//8 bit timer0: Toggle OC0A on Compare Match and CTC-Mode
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//for 847.5 kHz subcarrier
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//for 847.5 kHz subcarrier
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TCCR0A |= (1<<COM0A0) | (1<<WGM01);
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TCCR0A |= (1<<COM0A0) | (1<<WGM01);
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//set up 847.5 kHz subcarrier for sending (8 bit timer0)
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//set up 847.5 kHz subcarrier for sending (8 bit timer0)
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OCR0A = SUBC_OVF;
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OCR0A = SUBC_OVF;
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//CTC-Mode and no clock divider for 16 bit timer1: clk/1
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//CTC-Mode and no clock divider for 16 bit timer1: clk/1
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TCCR1B = (1<<WGM12) | (1<<CS10);
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TCCR1B = (1<<WGM12) | (1<<CS10);
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//Setup Analog Comparator, Enable (ACD), Set Analog Comparator
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//Setup Analog Comparator, Enable (ACD), Set Analog Comparator
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//Interrupt Flag on Rising Output Edge (ACIS0, ACIS1)
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//Interrupt Flag on Rising Output Edge (ACIS0, ACIS1)
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ACSR = (0<<ACD) | (1<<ACIS0) | (1<<ACIS1);
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ACSR = (0<<ACD) | (1<<ACIS0) | (1<<ACIS1);
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addCrc16(HLTA);
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addCrc16(HLTA);
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addBcc(CT_UID1);
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addBcc(CT_UID1);
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addBcc(UID2);
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addBcc(UID2);
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stoSize = storageSize;
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stoSize = storageSize;
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sto = storage;
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sto = storage;
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}
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}
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void addCrc16(uint8_t *Data, uint8_t Length)
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void addCrc16(uint8_t *Data, uint8_t Length)
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{
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{
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uint8_t ch;
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uint8_t ch;
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uint16_t wCrc = 0x6363; // ITU-V.41
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uint16_t wCrc = 0x6363; // ITU-V.41
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do {
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do {
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ch = *Data++;
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ch = *Data++;
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ch = (ch^(uint8_t)((wCrc) & 0x00FF));
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ch = (ch^(uint8_t)((wCrc) & 0x00FF));
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ch = (ch^(ch<<4));
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ch = (ch^(ch<<4));
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wCrc = (wCrc >> 8)^((uint16_t)ch << 8)^((uint16_t)ch<<3)^((uint16_t)ch>>4);
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wCrc = (wCrc >> 8)^((uint16_t)ch << 8)^((uint16_t)ch<<3)^((uint16_t)ch>>4);
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} while (--Length);
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} while (--Length);
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*Data = (uint8_t) (wCrc & 0xFF);
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*Data = (uint8_t) (wCrc & 0xFF);
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Data++;
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Data++;
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*Data = (uint8_t) ((wCrc >> 8) & 0xFF);
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*Data = (uint8_t) ((wCrc >> 8) & 0xFF);
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}
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}
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void addBcc(uint8_t *Data) //add exclusive-OR of 4 bytes
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void addBcc(uint8_t *Data) //add exclusive-OR of 4 bytes
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{
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{
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Data[4] = Data[0] ^ Data[1] ^ Data[2] ^ Data[3];
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Data[4] = Data[0] ^ Data[1] ^ Data[2] ^ Data[3];
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}
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}
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void waitForBitend()
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void waitForBitend()
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{
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{
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while(!(TIFR1 & (1<<OCF1A))); //Wait till end of bit-time
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while(!(TIFR1 & (1<<OCF1A))); //Wait till end of bit-time
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TIFR1 |= (1<<OCF1A);
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TIFR1 |= (1<<OCF1A);
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}
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}
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#if (F_CPU == RFID_FREQU)
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#if (F_CPU == RFID_FREQU)
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void waitForOneBitTime()
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void waitForOneBitTime()
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{
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{
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waitForBitend();
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waitForBitend();
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}
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}
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#elif (F_CPU == 22000000UL)
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#elif (F_CPU == 22000000UL)
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//Skip every 17 bit times 1 cycle
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//Skip every 17 bit times 1 cycle
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void waitForOneBitTime()
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void waitForOneBitTime()
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{
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{
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if (rCount < 17)
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if (rCount < 7)
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{
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{
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OCR1AL = CLC_PBIT / 2 - 1;
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OCR1AL = CLC_PBIT / 2 - 1;
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rCount++;
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rCount++;
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}
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}
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else
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else
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{
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{
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OCR1AL = CLC_PBIT / 2 - 2;
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OCR1AL = CLC_PBIT / 2 - 2;
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rCount = 0;
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rCount = 0;
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}
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}
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waitForBitend();
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waitForBitend();
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}
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}
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#elif (F_CPU == 13592500UL)
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#elif (F_CPU == 13592500UL)
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//Add every 6 bit times 1 cycle
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//Add every 6 bit times 1 cycle
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void waitForOneBitTime()
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void waitForOneBitTime()
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{
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{
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if (rCount < 6)
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if (rCount < 6)
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{
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{
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OCR1AL = CLC_PBIT / 2 - 1;
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OCR1AL = CLC_PBIT / 2 - 1;
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rCount++;
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rCount++;
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}
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}
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else
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else
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{
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{
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OCR1AL = CLC_PBIT / 2;
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OCR1AL = CLC_PBIT / 2;
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rCount = 0;
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rCount = 0;
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}
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}
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waitForBitend();
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waitForBitend();
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}
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}
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#else
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#else
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#error "Not supported frequency, please add support if possible"
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#error "Not supported frequency, please add support if possible"
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#endif
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#endif
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void txManchester(uint8_t *data, uint8_t length)
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void txManchester(uint8_t *data, uint8_t length)
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{
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{
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uint8_t txBytePos = 0;
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uint8_t txBytePos = 0;
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uint8_t txbitPos = 0;
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uint8_t txbitPos = 0;
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uint8_t parity = 0;
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uint8_t parity = 0;
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TIFR1 |= (1<<OCF1A);
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TIFR1 |= (1<<OCF1A);
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//Send SOC
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//Send SOC
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waitForBitend();
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waitForBitend();
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DDRB |= (1<<2);
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DDRB |= (1<<2);
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OCR1A = CLC_PBIT / 2 - 1; //Set Hi- and Low-Bit
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OCR1A = CLC_PBIT / 2 - 1; //Set Hi- and Low-Bit
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB &= ~(1<<2);
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DDRB &= ~(1<<2);
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do
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do
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{
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{
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if (TX_MASK[txbitPos] & data[txBytePos])
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if (TX_MASK[txbitPos] & data[txBytePos])
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{
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{
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB |= (1<<2);
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DDRB |= (1<<2);
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parity ^= 1;
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parity ^= 1;
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB &= ~(1<<2);
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DDRB &= ~(1<<2);
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}
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}
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else
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else
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{
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{
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB &= ~(1<<2);
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DDRB &= ~(1<<2);
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB |= (1<<2);
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DDRB |= (1<<2);
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}
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}
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txbitPos++;
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txbitPos++;
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if (txbitPos > 7)
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if (txbitPos > 7)
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{
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{
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if (parity)
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if (parity)
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{
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{
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB &= ~(1<<2);
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DDRB &= ~(1<<2);
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB |= (1<<2);
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DDRB |= (1<<2);
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}
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}
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else
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else
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{
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{
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB |= (1<<2);
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DDRB |= (1<<2);
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB &= ~(1<<2);
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DDRB &= ~(1<<2);
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}
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}
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txBytePos++;
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txBytePos++;
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txbitPos=0;
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txbitPos=0;
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parity = 0;
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parity = 0;
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}
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}
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}
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}
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while(txBytePos < length);
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while(txBytePos < length);
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//Send EOC
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//Send EOC
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waitForOneBitTime();
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waitForOneBitTime();
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DDRB &= ~(1<<2);
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DDRB &= ~(1<<2);
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}
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}
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inline void resetRxFlags()
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inline void resetRxFlags()
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{
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{
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TCNT1 = 0;
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TCNT1 = 0;
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TIFR1 |= (1<<OCF1A); //Clear Timer Overflow Flag
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TIFR1 |= (1<<OCF1A); //Clear Timer Overflow Flag
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ACSR |= (1<<ACI); //Clear Analog Comparator Interrupt Flag
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ACSR |= (1<<ACI); //Clear Analog Comparator Interrupt Flag
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}
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}
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uint8_t rxMiller()
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uint8_t rxMiller()
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{
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{
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uint8_t t;
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#if (F_CPU > 16000000)
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uint16_t cDown = 0xFFF;
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uint16_t t; //For hi cpu clock a 8 bit variable will overflow (CLCM > 0xFF)
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uint8_t bytePos = 0;
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#else
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uint8_t hbitPos = 0;
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uint8_t t; //For low cpu clock computing time is to low for 16bit a variable
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#endif
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OCR1A = CLCL-1;
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buffer[0] = 0;
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uint16_t cDown = 0x0FFF;
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uint8_t bytePos = 0;
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//Wait for transmission end if there is data arriving
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uint8_t hbitPos = 0;
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do
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{
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OCR1A = CLCL-1;
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if (ACSR & (1<<ACI)) resetRxFlags();
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buffer[0] = 0;
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}
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while(~TIFR1 & (1<<OCF1A));
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//Wait for transmission end if there is data arriving
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do
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//Wait for transmission end if there is data arriving
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{
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do
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if (ACSR & (1<<ACI)) resetRxFlags();
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{
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}
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if (TIFR1 & (1<<OCF1A))
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while(~TIFR1 & (1<<OCF1A));
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{
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TCNT1 = 0;
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//Wait for transmission end if there is data arriving
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TIFR1 |= (1<<OCF1A);
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do
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cDown--;
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{
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if (!cDown) break;
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if (TIFR1 & (1<<OCF1A))
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}
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{
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}
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TCNT1 = 0;
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while(~ACSR & (1<<ACI));
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TIFR1 |= (1<<OCF1A);
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cDown--;
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if (cDown)
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if (!cDown) break;
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{
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}
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resetRxFlags();
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}
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do
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while(~ACSR & (1<<ACI));
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{
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if ((ACSR & (1<<ACI)) && (TCNT1 > CMIN))
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if (cDown)
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{
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{
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t = TCNT1;
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resetRxFlags();
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resetRxFlags();
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do
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{
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hbitPos += (t > CLCS) + (t > CLCM);
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if ((ACSR & (1<<ACI)) && (TCNT1 > 1))
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{
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if(hbitPos > 17)
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t = TCNT1;
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{
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resetRxFlags();
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bytePos++;
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hbitPos -= 18;
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hbitPos += (t > CLCS) + (t > CLCM);
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buffer[bytePos] = 0;
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}
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if(hbitPos > 17)
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{
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buffer[bytePos] |= RX_MASK[hbitPos];
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bytePos++;
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hbitPos -= 18;
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hbitPos += 2;
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buffer[bytePos] = 0;
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} //34 or 41 (hbitPos > 17) click cycles
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}
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}
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while(~TIFR1 & (1<<OCF1A));
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buffer[bytePos] |= RX_MASK[hbitPos];
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}
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hbitPos += 2;
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OCR1A = FDT_DELAY[hbitPos & 1]; //Set delay for answer
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} //34 or 41 (hbitPos > 17) click cycles
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||||||
TIFR1 |= (1<<OCF1A);
|
}
|
||||||
|
while(~TIFR1 & (1<<OCF1A));
|
||||||
if (hbitPos > 7) bytePos++;
|
}
|
||||||
|
|
||||||
return bytePos;
|
OCR1A = FDT_DELAY[hbitPos & 1]; //Set delay for answer
|
||||||
}
|
TIFR1 |= (1<<OCF1A);
|
||||||
|
|
||||||
void sendData(uint8_t block)
|
if (hbitPos > 7) bytePos++;
|
||||||
{
|
|
||||||
uint8_t i = 0;
|
return bytePos;
|
||||||
uint16_t pos = (uint16_t)block * 4;
|
}
|
||||||
|
|
||||||
for(i=0; i < 16; i++)
|
void sendData(uint8_t block)
|
||||||
{
|
{
|
||||||
if (pos >= stoSize)
|
uint8_t i = 0;
|
||||||
{
|
uint16_t pos = (uint16_t)block * 4;
|
||||||
buffer[i] = 0;
|
|
||||||
}
|
for(i=0; i < 16; i++)
|
||||||
else
|
{
|
||||||
{
|
if (pos >= stoSize)
|
||||||
buffer[i] = sto[pos];
|
{
|
||||||
}
|
buffer[i] = 0;
|
||||||
|
}
|
||||||
pos++;
|
else
|
||||||
}
|
{
|
||||||
|
buffer[i] = sto[pos];
|
||||||
addCrc16(buffer, 16);
|
}
|
||||||
txManchester(buffer, 18);
|
|
||||||
}
|
pos++;
|
||||||
|
}
|
||||||
void receiveData(uint8_t block)
|
|
||||||
{
|
addCrc16(buffer, 16);
|
||||||
uint8_t i = 0;
|
txManchester(buffer, 18);
|
||||||
uint16_t pos = (uint16_t)block * 4;
|
}
|
||||||
uint8_t crc1 = buffer[6];
|
|
||||||
uint8_t crc2 = buffer[7];
|
void receiveData(uint8_t block)
|
||||||
|
{
|
||||||
addCrc16(buffer, 6);
|
uint8_t i = 0;
|
||||||
|
uint16_t pos = (uint16_t)block * 4;
|
||||||
if (buffer[6] == crc1 && buffer[7] == crc2)
|
uint8_t crc1 = buffer[6];
|
||||||
{
|
uint8_t crc2 = buffer[7];
|
||||||
for(i=2; i < 6; i++) //byte 2-5 contains Data
|
|
||||||
{
|
addCrc16(buffer, 6);
|
||||||
if (pos < stoSize) sto[pos] = buffer[i];
|
|
||||||
pos++;
|
if (buffer[6] == crc1 && buffer[7] == crc2)
|
||||||
}
|
{
|
||||||
|
for(i=2; i < 6; i++) //byte 2-5 contains Data
|
||||||
buffer[0] = 0x0A; //ACK
|
{
|
||||||
txManchester(buffer, 1);
|
if (pos < stoSize) sto[pos] = buffer[i];
|
||||||
}
|
pos++;
|
||||||
else
|
}
|
||||||
{
|
|
||||||
buffer[0] = 0x01; //NAK for CRC error
|
buffer[0] = 0x0A; //ACK
|
||||||
txManchester(buffer, 1);
|
txManchester(buffer, 1);
|
||||||
}
|
}
|
||||||
}
|
else
|
||||||
|
{
|
||||||
void checkForNfcReader()
|
buffer[0] = 0x01; //NAK for CRC error
|
||||||
{
|
txManchester(buffer, 1);
|
||||||
uint8_t bytes = 1;
|
}
|
||||||
uint8_t state = 0;
|
}
|
||||||
uint8_t cdow = 8;
|
|
||||||
|
void checkForNfcReader()
|
||||||
if (ACSR & (1<<ACI)) //13.56 MHz carrier available?
|
{
|
||||||
{
|
uint8_t bytes = 1;
|
||||||
AIN1_PRNG &= ~(1<<AIN1_PORT); //Deactivate pull up to increase sensitivity
|
uint8_t state = 0;
|
||||||
|
uint8_t cdow = 8;
|
||||||
while(cdow > 0)
|
|
||||||
{
|
if (ACSR & (1<<ACI)) //13.56 MHz carrier available?
|
||||||
bytes = rxMiller();
|
{
|
||||||
|
AIN1_PORT &= ~(1<<AIN1_BIT); //Deactivate pull up to increase sensitivity
|
||||||
if ((state & 7) == S_READY)
|
|
||||||
{
|
while(cdow > 0)
|
||||||
if (buffer[0] == SEL_CL1[0] && buffer[1] == SEL_CL1[1] )
|
{
|
||||||
{
|
bytes = rxMiller();
|
||||||
txManchester(CT_UID1, sizeof(CT_UID1));
|
|
||||||
}
|
if ((state & 7) == S_READY)
|
||||||
else if (buffer[0] == SEL_CL2[0] && buffer[1] == SEL_CL2[1] )
|
{
|
||||||
{
|
if (buffer[0] == SEL_CL1[0] && buffer[1] == SEL_CL1[1] )
|
||||||
txManchester(UID2, sizeof(UID2));
|
{
|
||||||
}
|
txManchester(CT_UID1, sizeof(CT_UID1));
|
||||||
else if (buffer[0] == SEL_CL1[0] && buffer[1] == 0x70 )
|
}
|
||||||
{
|
else if (buffer[0] == SEL_CL2[0] && buffer[1] == SEL_CL2[1] )
|
||||||
txManchester(SAK_NC, sizeof(SAK_NC));
|
{
|
||||||
}
|
txManchester(UID2, sizeof(UID2));
|
||||||
else if (buffer[0] == SEL_CL2[0] && buffer[1] == 0x70 )
|
}
|
||||||
{
|
else if (buffer[0] == SEL_CL1[0] && buffer[1] == 0x70 )
|
||||||
txManchester(SAK_C, sizeof(SAK_C));
|
{
|
||||||
state++; //Set state to ACTIVE
|
txManchester(SAK_NC, sizeof(SAK_NC));
|
||||||
}
|
}
|
||||||
else
|
else if (buffer[0] == SEL_CL2[0] && buffer[1] == 0x70 )
|
||||||
{
|
{
|
||||||
state &= 8; //Set state to IDLE/HALT
|
txManchester(SAK_C, sizeof(SAK_C));
|
||||||
}
|
state++; //Set state to ACTIVE
|
||||||
}
|
}
|
||||||
else if ((state & 7) == S_ACTIVE)
|
else
|
||||||
{
|
{
|
||||||
if (buffer[0] == READ[0])
|
state &= 8; //Set state to IDLE/HALT
|
||||||
{
|
}
|
||||||
sendData(buffer[1]);
|
}
|
||||||
}
|
else if ((state & 7) == S_ACTIVE)
|
||||||
else if (buffer[0] == WRITE[0])
|
{
|
||||||
{
|
if (buffer[0] == READ[0])
|
||||||
receiveData(buffer[1]);
|
{
|
||||||
}
|
sendData(buffer[1]);
|
||||||
else if (buffer[0] == HLTA[0] && buffer[2] == HLTA[2] )
|
}
|
||||||
{
|
else if (buffer[0] == WRITE[0])
|
||||||
state = S_HALT;
|
{
|
||||||
}
|
receiveData(buffer[1]);
|
||||||
else if(bytes)
|
}
|
||||||
{
|
else if (buffer[0] == HLTA[0] && buffer[2] == HLTA[2] )
|
||||||
state &= 8; //Set state to IDLE/HALT
|
{
|
||||||
}
|
state = S_HALT;
|
||||||
}
|
}
|
||||||
else if (bytes == 1 && (buffer[0] == REQA[0] || buffer[0] == WUPA[0])) //state == S_IDLE
|
else if(bytes)
|
||||||
{
|
{
|
||||||
txManchester(ATQA, sizeof(ATQA));
|
state &= 8; //Set state to IDLE/HALT
|
||||||
state = (state & 8) + S_READY; //Set state to READY
|
}
|
||||||
}
|
}
|
||||||
|
else if (bytes == 1 && (buffer[0] == REQA[0] || buffer[0] == WUPA[0])) //state == S_IDLE
|
||||||
cdow -= (bytes == 0);
|
{
|
||||||
}
|
txManchester(ATQA, sizeof(ATQA));
|
||||||
AIN1_PRNG |= (1<<AIN1_PORT); //Activate pull up to prevent noise from toggling the comparator
|
state = (state & 8) + S_READY; //Set state to READY
|
||||||
}
|
}
|
||||||
ACSR |= (1<<ACI); //Clear comparator interrupt flag
|
|
||||||
|
cdow -= (bytes == 0);
|
||||||
|
}
|
||||||
|
AIN1_PORT |= (1<<AIN1_BIT); //Activate pull up to prevent noise from toggling the comparator
|
||||||
|
}
|
||||||
|
ACSR |= (1<<ACI); //Clear comparator interrupt flag
|
||||||
}
|
}
|
||||||
Loading…
Reference in New Issue