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relocation data for ARM updated

This commit is contained in:
Nicolas 2026-01-27 14:47:52 +01:00
parent 024f86d4bc
commit 7376e505d5
1 changed files with 35 additions and 25 deletions
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60
src/pelfy/_fields_data.py
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@ -389,39 +389,49 @@ relocation_table_types = {
33: ("R_AMD64_SIZE64", 64, "Z + A"), 33: ("R_AMD64_SIZE64", 64, "Z + A"),
}, },
"EM_ARM": { "EM_ARM": {
0: ("R_ARM_NONE", 0, ""), 0: ("R_ARM_NONE", 0, ""),
1: ("R_ARM_PC24", 24, "S - P + A"),
2: ("R_ARM_ABS32", 32, "S + A"), 1: ("R_ARM_PC24", 24, "S - P + A"),
3: ("R_ARM_REL32", 32, "S - P + A"), 2: ("R_ARM_ABS32", 32, "S + A"),
4: ("R_ARM_PC13", 13, "S - P + A"), 3: ("R_ARM_REL32", 32, "S - P + A"),
5: ("R_ARM_ABS16", 16, "S + A"), 4: ("R_ARM_LDR_PC_G0", 12, "S - P + A"),
6: ("R_ARM_ABS12", 12, "S + A"),
7: ("R_ARM_THM_ABS5", 5, "S + A"), 5: ("R_ARM_ABS16", 16, "S + A"),
8: ("R_ARM_ABS8", 8, "S + A"), 6: ("R_ARM_ABS12", 12, "S + A"),
9: ("R_ARM_SBREL32", 32, "S - B + A"), 7: ("R_ARM_THM_ABS5", 5, "S + A"),
10: ("R_ARM_THM_PC22", 22, "S - P + A"), 8: ("R_ARM_ABS8", 8, "S + A"),
9: ("R_ARM_SBREL32", 32, "S - B + A"),
10: ("R_ARM_THM_CALL", 22, "S - P + A"),
11: ("R_ARM_THM_PC8", 8, "S - P + A"), 11: ("R_ARM_THM_PC8", 8, "S - P + A"),
12: ("Reserved", 0, ""), 12: ("R_ARM_BREL_ADJ", 0, ""),
13: ("R_ARM_SWI24", 24, "S + A"), 13: ("R_ARM_TLS_DESC", 0, ""),
14: ("R_ARM_THM_SWI8", 8, "S + A"), 14: ("R_ARM_THM_SWI8", 8, "S + A"),
15: ("R_ARM_XPC25", 25, ""), 15: ("R_ARM_XPC25", 25, ""),
16: ("R_ARM_THM_XPC22", 22, ""), 16: ("R_ARM_THM_XPC22", 22, ""),
28: ("R_ARM_CALL", 24, "((S + A) - P) >> 2"), 28: ("R_ARM_CALL", 24, "((S + A) - P) >> 2"),
29: ("R_ARM_JUMP24", 24, "((S + A) - P) >> 2"), 29: ("R_ARM_JUMP24", 24, "((S + A) - P) >> 2"),
30: ("R_ARM_TLS_DESC", 0, ""), 30: ("R_ARM_THM_JUMP24", 24, "((S + A) - P) >> 1"),
32: ("R_ARM_ALU_PCREL_7_0", 7, "(S - P + A) & 0x000000FF"),
33: ("R_ARM_ALU_PCREL_15_8", 15, "(S - P + A) & 0x0000FF00"), 32: ("R_ARM_ALU_PCREL_7_0", 8, "(S - P + A) & 0x000000FF"),
34: ("R_ARM_ALU_PCREL_23_15", 23, "(S - P + A) & 0x00FF0000"), 33: ("R_ARM_ALU_PCREL_15_8", 8, "(S - P + A) & 0x0000FF00"),
35: ("R_ARM_LDR_SBREL_11_0", 11, "(S - B + A) & 0x00000FFF"), 34: ("R_ARM_ALU_PCREL_23_15", 9, "(S - P + A) & 0x00FF8000"),
36: ("R_ARM_ALU_SBREL_19_12", 19, "(S - B + A) & 0x000FF000"),
37: ("R_ARM_ALU_SBREL_27_20", 27, "(S - B + A) & 0x0FF00000"), 35: ("R_ARM_LDR_SBREL_11_0", 12, "(S - B + A) & 0x00000FFF"),
38: ("R_ARM_RELABS32", 32, "S + A or S - P + A"), 36: ("R_ARM_ALU_SBREL_19_12", 8, "(S - B + A) & 0x000FF000"),
39: ("R_ARM_ROSEGREL32", 32, "S - E + A"), 37: ("R_ARM_ALU_SBREL_27_20", 8, "(S - B + A) & 0x0FF00000"),
38: ("R_ARM_TARGET1", 32, "implementation defined"),
39: ("R_ARM_SBREL31", 31, "S - B + A"),
40: ("R_ARM_V4BX", 0, ""), 40: ("R_ARM_V4BX", 0, ""),
41: ("R_ARM_STKCHK", 0, ""), 41: ("R_ARM_TARGET2", 32, "implementation defined"),
42: ("R_ARM_THM_STKCHK", 0, ""), 42: ("R_ARM_PREL31", 31, "S - P + A"),
43: ("R_ARM_MOVW_ABS_NC", 16, "S + A"), 43: ("R_ARM_MOVW_ABS_NC", 16, "S + A"),
44: ("R_ARM_MOVT_ABS", 16, "S + A") 44: ("R_ARM_MOVT_ABS", 16, "S + A"),
}, },
"EM_AARCH64": { "EM_AARCH64": {
0: ("R_AARCH64_NONE", 0, ""), 0: ("R_AARCH64_NONE", 0, ""),