Below is an in-depth explanation of the AArch64 (ARM64) unconditional branch instruction—often simply called the “B” instruction—and how its 26‐bit immediate field (imm26) is laid out and later relocated during linking.

Instruction Layout

The unconditional branch in AArch64 is encoded in a 32‑bit instruction. Its layout is as follows:

Bits:  31         26 25                           0
        +-------------+------------------------------+
        |  Opcode     |          imm26               |
        +-------------+------------------------------+

• Opcode (bits 31:26):
• For a plain branch (B), the opcode is 000101.

• For a branch with link (BL), which saves the return address (i.e., a call), the opcode is 100101. These 6 bits determine the instruction type.

• Immediate Field (imm26, bits 25:0):

• This 26‑bit field holds a signed immediate value.

• Offset Calculation: At runtime, the processor:

  1. Shifts the 26‑bit immediate left by 2 bits. (Because instructions are 4-byte aligned, the two least-significant bits are always zero.)
  2. Sign-extends the resulting 28‑bit value to the full register width (typically 64 bits).
  3. Adds this value to the program counter (PC) to obtain the branch target.

• Reach:

• With a 26‑bit signed field that’s effectively 28 bits after the shift, the branch can cover a range of approximately ±128 MB from the current instruction.