From 700813ff31c4f621d9d3830f0f7ce36ba1308f20 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Tue, 27 Jan 2026 13:40:50 +0100 Subject: [PATCH 01/15] Version bumped to 1.0.8 --- pyproject.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pyproject.toml b/pyproject.toml index fc4520e..d3839e2 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,6 +1,6 @@ [project] name = "pelfy" -version = "1.0.7" +version = "1.0.8" authors = [ { name="Nicolas Kruse", email="nicolas.kruse@nonan.net" }, ] From 024f86d4bcee3a7b0ee9c20331d695ab1922fd5a Mon Sep 17 00:00:00 2001 From: Nicolas Date: Tue, 27 Jan 2026 13:52:33 +0100 Subject: [PATCH 02/15] size attribute added to symbol class --- src/pelfy/_main.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index 206a2aa..1bf7291 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -42,6 +42,7 @@ class elf_symbol(): offset_in_section: Position of first symbol byte relative to section start offset_in_file: Position of first symbol byte in object file + size: size of symbol in bytes fields: All symbol header fields as dict """ @@ -71,6 +72,7 @@ class elf_symbol(): self.thumb_mode = bool((file.architecture == 'EM_ARM') & fields['st_value'] & 1) self.offset_in_section = fields['st_value'] & ~int(self.thumb_mode) self.offset_in_file = self.section['sh_offset'] + self.offset_in_section if self.section else 0 + self.size = self.fields['st_size'] @property def data(self) -> bytes: From 7376e505d526d19b17158233f3e40fd029c7c6e4 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Tue, 27 Jan 2026 14:47:52 +0100 Subject: [PATCH 03/15] relocation data for ARM updated --- src/pelfy/_fields_data.py | 60 +++++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/src/pelfy/_fields_data.py b/src/pelfy/_fields_data.py index f489095..459f7ea 100644 --- a/src/pelfy/_fields_data.py +++ b/src/pelfy/_fields_data.py @@ -389,39 +389,49 @@ relocation_table_types = { 33: ("R_AMD64_SIZE64", 64, "Z + A"), }, "EM_ARM": { - 0: ("R_ARM_NONE", 0, ""), - 1: ("R_ARM_PC24", 24, "S - P + A"), - 2: ("R_ARM_ABS32", 32, "S + A"), - 3: ("R_ARM_REL32", 32, "S - P + A"), - 4: ("R_ARM_PC13", 13, "S - P + A"), - 5: ("R_ARM_ABS16", 16, "S + A"), - 6: ("R_ARM_ABS12", 12, "S + A"), - 7: ("R_ARM_THM_ABS5", 5, "S + A"), - 8: ("R_ARM_ABS8", 8, "S + A"), - 9: ("R_ARM_SBREL32", 32, "S - B + A"), - 10: ("R_ARM_THM_PC22", 22, "S - P + A"), + 0: ("R_ARM_NONE", 0, ""), + + 1: ("R_ARM_PC24", 24, "S - P + A"), + 2: ("R_ARM_ABS32", 32, "S + A"), + 3: ("R_ARM_REL32", 32, "S - P + A"), + 4: ("R_ARM_LDR_PC_G0", 12, "S - P + A"), + + 5: ("R_ARM_ABS16", 16, "S + A"), + 6: ("R_ARM_ABS12", 12, "S + A"), + 7: ("R_ARM_THM_ABS5", 5, "S + A"), + 8: ("R_ARM_ABS8", 8, "S + A"), + 9: ("R_ARM_SBREL32", 32, "S - B + A"), + + 10: ("R_ARM_THM_CALL", 22, "S - P + A"), 11: ("R_ARM_THM_PC8", 8, "S - P + A"), - 12: ("Reserved", 0, ""), - 13: ("R_ARM_SWI24", 24, "S + A"), + 12: ("R_ARM_BREL_ADJ", 0, ""), + 13: ("R_ARM_TLS_DESC", 0, ""), 14: ("R_ARM_THM_SWI8", 8, "S + A"), + 15: ("R_ARM_XPC25", 25, ""), 16: ("R_ARM_THM_XPC22", 22, ""), + 28: ("R_ARM_CALL", 24, "((S + A) - P) >> 2"), 29: ("R_ARM_JUMP24", 24, "((S + A) - P) >> 2"), - 30: ("R_ARM_TLS_DESC", 0, ""), - 32: ("R_ARM_ALU_PCREL_7_0", 7, "(S - P + A) & 0x000000FF"), - 33: ("R_ARM_ALU_PCREL_15_8", 15, "(S - P + A) & 0x0000FF00"), - 34: ("R_ARM_ALU_PCREL_23_15", 23, "(S - P + A) & 0x00FF0000"), - 35: ("R_ARM_LDR_SBREL_11_0", 11, "(S - B + A) & 0x00000FFF"), - 36: ("R_ARM_ALU_SBREL_19_12", 19, "(S - B + A) & 0x000FF000"), - 37: ("R_ARM_ALU_SBREL_27_20", 27, "(S - B + A) & 0x0FF00000"), - 38: ("R_ARM_RELABS32", 32, "S + A or S - P + A"), - 39: ("R_ARM_ROSEGREL32", 32, "S - E + A"), + 30: ("R_ARM_THM_JUMP24", 24, "((S + A) - P) >> 1"), + + 32: ("R_ARM_ALU_PCREL_7_0", 8, "(S - P + A) & 0x000000FF"), + 33: ("R_ARM_ALU_PCREL_15_8", 8, "(S - P + A) & 0x0000FF00"), + 34: ("R_ARM_ALU_PCREL_23_15", 9, "(S - P + A) & 0x00FF8000"), + + 35: ("R_ARM_LDR_SBREL_11_0", 12, "(S - B + A) & 0x00000FFF"), + 36: ("R_ARM_ALU_SBREL_19_12", 8, "(S - B + A) & 0x000FF000"), + 37: ("R_ARM_ALU_SBREL_27_20", 8, "(S - B + A) & 0x0FF00000"), + + 38: ("R_ARM_TARGET1", 32, "implementation defined"), + 39: ("R_ARM_SBREL31", 31, "S - B + A"), + 40: ("R_ARM_V4BX", 0, ""), - 41: ("R_ARM_STKCHK", 0, ""), - 42: ("R_ARM_THM_STKCHK", 0, ""), + 41: ("R_ARM_TARGET2", 32, "implementation defined"), + 42: ("R_ARM_PREL31", 31, "S - P + A"), + 43: ("R_ARM_MOVW_ABS_NC", 16, "S + A"), - 44: ("R_ARM_MOVT_ABS", 16, "S + A") + 44: ("R_ARM_MOVT_ABS", 16, "S + A"), }, "EM_AARCH64": { 0: ("R_AARCH64_NONE", 0, ""), From aab7f83cd97ad3404059a00805773cd62bdcd8fb Mon Sep 17 00:00:00 2001 From: Nicolas Date: Tue, 27 Jan 2026 14:48:41 +0100 Subject: [PATCH 04/15] _get_rel_addend function updated for ARM in thumb mode --- src/pelfy/_main.py | 53 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index 1bf7291..5b1047b 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -26,6 +26,53 @@ def open_elf_file(file_path: str) -> 'elf_file': return elf_file(f.read()) +def _decode_thumb_branch_imm(field: int, bits: int): + """ + Decode Thumb-2 wide branch immediate. + bits: 22 (R_ARM_THM_PC22) or 24 (R_ARM_THM_JUMP24) + """ + + h1 = (field >> 16) & 0xFFFF + h2 = field & 0xFFFF + + S = (h1 >> 10) & 1 + imm10 = h1 & 0x03FF + J1 = (h2 >> 13) & 1 + J2 = (h2 >> 11) & 1 + imm11 = h2 & 0x07FF + + # Decode J1/J2 → I1/I2 + I1 = (~(J1 ^ S)) & 1 + I2 = (~(J2 ^ S)) & 1 + + if bits == 24: + imm = ( + (S << 23) | + (I1 << 22) | + (I2 << 21) | + (imm10 << 11) | + (imm11 << 0) + ) + sign_bit = 23 + else: + assert bits == 22 + imm = ( + (S << 21) | + (I1 << 20) | + (I2 << 19) | + (imm10 << 9) | + (imm11 << 0) + ) + sign_bit = 21 + + # Sign extend + if imm & (1 << sign_bit): + imm |= ~((1 << (sign_bit + 1)) - 1) + + # Thumb branch offsets are halfword aligned + return imm << 1 + + class elf_symbol(): """A class for representing data of an ELF symbol @@ -546,8 +593,12 @@ class elf_file: if imm24 & 0x800000: imm24 |= ~0xFFFFFF return imm24 << 2 + if name == 'R_ARM_THM_PC22': + return _decode_thumb_branch_imm(field, 22) + if name in ('R_ARM_THM_JUMP24', 'R_ARM_THM_CALL'): + return _decode_thumb_branch_imm(field, 24) if '_THM_' in name: - print('Warning: Thumb relocation addend extraction is not implemented') + print(f'Warning: Thumb relocation addend extraction is for {name} not implemented') return 0 if '_MIPS_' in name: print('Warning: MIPS relocations addend extraction is not implemented') From 5f0c36fef4bc210fdb8ce18caa1ee89015549de4 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Tue, 27 Jan 2026 16:37:27 +0100 Subject: [PATCH 05/15] code style and typehints fixed --- src/pelfy/_fields_data.py | 22 +++++++++++----------- src/pelfy/_main.py | 8 ++++---- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/pelfy/_fields_data.py b/src/pelfy/_fields_data.py index 459f7ea..ce9cb1b 100644 --- a/src/pelfy/_fields_data.py +++ b/src/pelfy/_fields_data.py @@ -389,18 +389,18 @@ relocation_table_types = { 33: ("R_AMD64_SIZE64", 64, "Z + A"), }, "EM_ARM": { - 0: ("R_ARM_NONE", 0, ""), + 0: ("R_ARM_NONE", 0, ""), - 1: ("R_ARM_PC24", 24, "S - P + A"), - 2: ("R_ARM_ABS32", 32, "S + A"), - 3: ("R_ARM_REL32", 32, "S - P + A"), - 4: ("R_ARM_LDR_PC_G0", 12, "S - P + A"), + 1: ("R_ARM_PC24", 24, "S - P + A"), + 2: ("R_ARM_ABS32", 32, "S + A"), + 3: ("R_ARM_REL32", 32, "S - P + A"), + 4: ("R_ARM_LDR_PC_G0", 12, "S - P + A"), - 5: ("R_ARM_ABS16", 16, "S + A"), - 6: ("R_ARM_ABS12", 12, "S + A"), - 7: ("R_ARM_THM_ABS5", 5, "S + A"), - 8: ("R_ARM_ABS8", 8, "S + A"), - 9: ("R_ARM_SBREL32", 32, "S - B + A"), + 5: ("R_ARM_ABS16", 16, "S + A"), + 6: ("R_ARM_ABS12", 12, "S + A"), + 7: ("R_ARM_THM_ABS5", 5, "S + A"), + 8: ("R_ARM_ABS8", 8, "S + A"), + 9: ("R_ARM_SBREL32", 32, "S - B + A"), 10: ("R_ARM_THM_CALL", 22, "S - P + A"), 11: ("R_ARM_THM_PC8", 8, "S - P + A"), @@ -415,7 +415,7 @@ relocation_table_types = { 29: ("R_ARM_JUMP24", 24, "((S + A) - P) >> 2"), 30: ("R_ARM_THM_JUMP24", 24, "((S + A) - P) >> 1"), - 32: ("R_ARM_ALU_PCREL_7_0", 8, "(S - P + A) & 0x000000FF"), + 32: ("R_ARM_ALU_PCREL_7_0", 8, "(S - P + A) & 0x000000FF"), 33: ("R_ARM_ALU_PCREL_15_8", 8, "(S - P + A) & 0x0000FF00"), 34: ("R_ARM_ALU_PCREL_23_15", 9, "(S - P + A) & 0x00FF8000"), diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index 5b1047b..15a86cd 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -26,7 +26,7 @@ def open_elf_file(file_path: str) -> 'elf_file': return elf_file(f.read()) -def _decode_thumb_branch_imm(field: int, bits: int): +def _decode_thumb_branch_imm(field: int, bits: int) -> int: """ Decode Thumb-2 wide branch immediate. bits: 22 (R_ARM_THM_PC22) or 24 (R_ARM_THM_JUMP24) @@ -35,10 +35,10 @@ def _decode_thumb_branch_imm(field: int, bits: int): h1 = (field >> 16) & 0xFFFF h2 = field & 0xFFFF - S = (h1 >> 10) & 1 + S = (h1 >> 10) & 1 imm10 = h1 & 0x03FF - J1 = (h2 >> 13) & 1 - J2 = (h2 >> 11) & 1 + J1 = (h2 >> 13) & 1 + J2 = (h2 >> 11) & 1 imm11 = h2 & 0x07FF # Decode J1/J2 → I1/I2 From d7e7876afd787bf8062f9933851566a2c1481e82 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Tue, 27 Jan 2026 16:57:39 +0100 Subject: [PATCH 06/15] fixed usage of offset_in_section instead of st_value --- src/pelfy/_main.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index 15a86cd..bea2f66 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -124,15 +124,12 @@ class elf_symbol(): @property def data(self) -> bytes: """Returns the binary data the symbol is pointing to. - The offset in the ELF file is calculated by: - sections[symbol.st_shndx].sh_offset + symbol.st_value """ assert self.section, 'This symbol is not associated to a data section' if self.section.type == 'SHT_NOBITS': return b'\x00' * self['st_size'] else: - offset = self.section['sh_offset'] + self['st_value'] - return self.file.read_bytes(offset, self['st_size']) + return self.file.read_bytes(self.offset_in_file, self['st_size']) @property def data_hex(self) -> str: @@ -151,7 +148,7 @@ class elf_symbol(): assert self.section and self.section.type == 'SHT_PROGBITS' for reloc in self.file.get_relocations(): if reloc.target_section == self.section: - offset = reloc['r_offset'] - self['st_value'] + offset = reloc['r_offset'] - self.offset_in_section if 0 <= offset < self['st_size']: ret.append(reloc) return relocation_list(ret) From 86de67a7f8aa12141d42326c3ddd0e38b19fdb94 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Thu, 26 Feb 2026 10:20:13 +0100 Subject: [PATCH 07/15] Thumb relocations R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_ABS_NC added --- src/pelfy/_fields_data.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/pelfy/_fields_data.py b/src/pelfy/_fields_data.py index ce9cb1b..4a53181 100644 --- a/src/pelfy/_fields_data.py +++ b/src/pelfy/_fields_data.py @@ -432,6 +432,9 @@ relocation_table_types = { 43: ("R_ARM_MOVW_ABS_NC", 16, "S + A"), 44: ("R_ARM_MOVT_ABS", 16, "S + A"), + + 47: ("R_ARM_THM_MOVW_ABS_NC", 16, "S + A"), + 48: ("R_ARM_THM_MOVT_ABS_NC", 16, "S + A"), }, "EM_AARCH64": { 0: ("R_AARCH64_NONE", 0, ""), From 39bb639c1fd0865322172e0b210470b1d9ee4e30 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Fri, 27 Feb 2026 14:47:21 +0100 Subject: [PATCH 08/15] stencils_armv7thumb_O3_THM_MOVW.o test object added for thumb code using R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_ABS_NC instead of litteral pools. new addend extractions added, but untested --- src/pelfy/_main.py | 21 ++++++++++++++++++-- tests/obj/stencils_armv7thumb_O3_THM_MOVW.o | Bin 0 -> 42128 bytes 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 tests/obj/stencils_armv7thumb_O3_THM_MOVW.o diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index bea2f66..af2e15a 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -9,6 +9,7 @@ Typical usage example: from . import _fields_data as fdat from . import _output_formatter from typing import TypeVar, Literal, Iterable, Generic, Iterator, Generator, Optional, Union +import warnings _T = TypeVar('_T') @@ -594,11 +595,27 @@ class elf_file: return _decode_thumb_branch_imm(field, 22) if name in ('R_ARM_THM_JUMP24', 'R_ARM_THM_CALL'): return _decode_thumb_branch_imm(field, 24) + if name == 'R_ARM_THM_MOVW_ABS_NC': + # Extract addend for Thumb MOVW (lower 16 bits) + imm4 = (field >> 16) & 0xF + i = (field >> 26) & 0x1 + imm3 = (field >> 12) & 0x7 + imm8 = (field >> 0) & 0xFF + addend = (i << 11) | (imm4 << 12) | (imm3 << 8) | imm8 + return addend + if name == 'R_ARM_THM_MOVT_ABS_NC': + # Extract addend for Thumb MOVT (upper 16 bits) + imm4 = (field >> 16) & 0xF + i = (field >> 26) & 0x1 + imm3 = (field >> 12) & 0x7 + imm8 = (field >> 0) & 0xFF + addend = ((i << 11) | (imm4 << 12) | (imm3 << 8) | imm8) << 16 + return addend if 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z6}~2gZ#Cna2HXevGRXG&ncOm9`i(Og_(=9e#<#lz{;wh$ z&{mLqFEGC8bE0-R0$IuT9^-R&GXL)*&Uc8(ErZ-NDP-{x{EXFGjC%Vao!UXasxRwp zVSMj`PwGxQ(tas$4r-pfpYMm&Di+yzO)U~+z2`B$4GQ143g5+yZ@{@i(07+)kosN7__l&?ID|;Q6NsgL6B%D> zmN0(9kn*AqQ0= zLHgB&OfCSq332M3$mIIvpuKVAu48f&24LQeBX^S}XSXz}7#LB_xR6DD2RUlfFUi%! zk&|sCLV5jwRj*tVP`yWFCgiAI`fRr3WY&zqNK}HBqSE@eVgK#u&6{?`!6_X*=W3ch}E_?nqq$00(fzx6BY z4Y7Jxqh5L6qIY*?y(bypQSiBydZk^zWqcbHzHEgrDc$TB*>7n>h4GHEq$K_5(;jm0 z6*7ep_Cs!%1c*t70>yHy5q4b&{dx*P-{-8vhxDU%QJ+cQ!=> Date: Fri, 27 Feb 2026 15:02:55 +0100 Subject: [PATCH 09/15] Fixed name R_ARM_THM_MOVT_ABS_NC -> R_ARM_THM_MOVT_ABS --- src/pelfy/_fields_data.py | 2 +- src/pelfy/_main.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/pelfy/_fields_data.py b/src/pelfy/_fields_data.py index 4a53181..498f29d 100644 --- a/src/pelfy/_fields_data.py +++ b/src/pelfy/_fields_data.py @@ -434,7 +434,7 @@ relocation_table_types = { 44: ("R_ARM_MOVT_ABS", 16, "S + A"), 47: ("R_ARM_THM_MOVW_ABS_NC", 16, "S + A"), - 48: ("R_ARM_THM_MOVT_ABS_NC", 16, "S + A"), + 48: ("R_ARM_THM_MOVT_ABS", 16, "S + A"), }, "EM_AARCH64": { 0: ("R_AARCH64_NONE", 0, ""), diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index af2e15a..52521ec 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -603,7 +603,7 @@ class elf_file: imm8 = (field >> 0) & 0xFF addend = (i << 11) | (imm4 << 12) | (imm3 << 8) | imm8 return addend - if name == 'R_ARM_THM_MOVT_ABS_NC': + if name == 'R_ARM_THM_MOVT_ABS': # Extract addend for Thumb MOVT (upper 16 bits) imm4 = (field >> 16) & 0xF i = (field >> 26) & 0x1 From 20b00109e99ae5396705c1b1a62ffe9e319fe032 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Fri, 27 Feb 2026 17:57:28 +0100 Subject: [PATCH 10/15] Added test for 32 bit ARM relocations --- tests/obj/stencils_armv7_O3.asm | 4109 +++++++++++++++++++++++++++++++ tests/obj/stencils_armv7_O3.o | Bin 0 -> 42236 bytes tests/test_arm_addend.py | 65 + 3 files changed, 4174 insertions(+) create mode 100644 tests/obj/stencils_armv7_O3.asm create mode 100644 tests/obj/stencils_armv7_O3.o create mode 100644 tests/test_arm_addend.py diff --git a/tests/obj/stencils_armv7_O3.asm b/tests/obj/stencils_armv7_O3.asm new file mode 100644 index 0000000..2ddba9b --- /dev/null +++ b/tests/obj/stencils_armv7_O3.asm @@ -0,0 +1,4109 @@ + +src/copapy/obj/stencils_armv7_O3.o: file format elf32-littlearm +src/copapy/obj/stencils_armv7_O3.o +architecture: arm, flags 0x00000011: +HAS_RELOC, HAS_SYMS +start address 0x00000000 +private flags = 5000000: [Version5 EABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000014c 00000000 00000000 00000034 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .text.auxsub_get_42 00000018 00000000 00000000 00000180 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text.aux_get_42 0000001c 00000000 00000000 00000198 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 3 .text.entry_function_shell 00000020 00000000 00000000 000001b4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 4 .text.cast_float_int_int 00000010 00000000 00000000 000001d4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 5 .text.cast_float_int_float 00000010 00000000 00000000 000001e4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 6 .text.cast_int_float_int 00000010 00000000 00000000 000001f4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 7 .text.cast_int_float_float 00000010 00000000 00000000 00000204 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 8 .text.get_42_int 00000018 00000000 00000000 00000214 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 9 .text.get_42_float 00000010 00000000 00000000 0000022c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 10 .text.neg_int 00000008 00000000 00000000 0000023c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 11 .text.neg_float 00000008 00000000 00000000 00000244 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 12 .text.sqrt_int 00000038 00000000 00000000 0000024c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 13 .text.sqrt_float 00000030 00000000 00000000 00000284 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 14 .text.exp_int 00000018 00000000 00000000 000002b4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 15 .text.exp_float 00000010 00000000 00000000 000002cc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 16 .text.log_int 00000018 00000000 00000000 000002dc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 17 .text.log_float 00000010 00000000 00000000 000002f4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 18 .text.sin_int 00000018 00000000 00000000 00000304 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 19 .text.sin_float 00000010 00000000 00000000 0000031c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 20 .text.cos_int 00000018 00000000 00000000 0000032c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 21 .text.cos_float 00000010 00000000 00000000 00000344 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 22 .text.tan_int 00000018 00000000 00000000 00000354 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 23 .text.tan_float 00000010 00000000 00000000 0000036c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 24 .text.asin_int 00000018 00000000 00000000 0000037c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 25 .text.asin_float 00000010 00000000 00000000 00000394 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 26 .text.acos_int 00000018 00000000 00000000 000003a4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 27 .text.acos_float 00000010 00000000 00000000 000003bc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 28 .text.atan_int 00000018 00000000 00000000 000003cc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 29 .text.atan_float 00000010 00000000 00000000 000003e4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 30 .text.abs_float 00000008 00000000 00000000 000003f4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 31 .text.abs_int 0000000c 00000000 00000000 000003fc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 32 .text.sign_int 00000014 00000000 00000000 00000408 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 33 .text.sign_float 00000020 00000000 00000000 0000041c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 34 .text.atan2_int_int 00000030 00000000 00000000 0000043c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 35 .text.atan2_int_float 0000002c 00000000 00000000 0000046c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 36 .text.atan2_float_int 00000028 00000000 00000000 00000498 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 37 .text.atan2_float_float 00000020 00000000 00000000 000004c0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 38 .text.pow_int_int 00000030 00000000 00000000 000004e0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 39 .text.pow_int_float 0000002c 00000000 00000000 00000510 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 40 .text.pow_float_int 00000028 00000000 00000000 0000053c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 41 .text.pow_float_float 00000020 00000000 00000000 00000564 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 42 .text.min_int_int 0000000c 00000000 00000000 00000584 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 43 .text.max_int_int 0000000c 00000000 00000000 00000590 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 44 .text.min_int_float 0000001c 00000000 00000000 0000059c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 45 .text.max_int_float 0000001c 00000000 00000000 000005b8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 46 .text.min_float_int 00000018 00000000 00000000 000005d4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 47 .text.max_float_int 00000018 00000000 00000000 000005ec 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 48 .text.min_float_float 00000010 00000000 00000000 00000604 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 49 .text.max_float_float 00000010 00000000 00000000 00000614 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 50 .text.add_int_int 00000008 00000000 00000000 00000624 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 51 .text.add_int_float 00000014 00000000 00000000 0000062c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 52 .text.add_float_int 00000010 00000000 00000000 00000640 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 53 .text.add_float_float 00000008 00000000 00000000 00000650 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 54 .text.sub_int_int 00000008 00000000 00000000 00000658 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 55 .text.sub_int_float 00000014 00000000 00000000 00000660 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 56 .text.sub_float_int 00000010 00000000 00000000 00000674 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 57 .text.sub_float_float 00000008 00000000 00000000 00000684 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 58 .text.mul_int_int 00000008 00000000 00000000 0000068c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 59 .text.mul_int_float 00000014 00000000 00000000 00000694 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 60 .text.mul_float_int 00000010 00000000 00000000 000006a8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 61 .text.mul_float_float 00000008 00000000 00000000 000006b8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 62 .text.div_int_int 00000028 00000000 00000000 000006c0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 63 .text.div_int_float 00000014 00000000 00000000 000006e8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 64 .text.div_float_int 00000010 00000000 00000000 000006fc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 65 .text.div_float_float 00000008 00000000 00000000 0000070c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 66 .text.floordiv_int_int 00000030 00000000 00000000 00000714 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 67 .text.floordiv_int_float 0000002c 00000000 00000000 00000744 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 68 .text.floordiv_float_int 0000002c 00000000 00000000 00000770 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 69 .text.floordiv_float_float 00000024 00000000 00000000 0000079c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 70 .text.gt_int_int 00000010 00000000 00000000 000007c0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 71 .text.gt_int_float 0000001c 00000000 00000000 000007d0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 72 .text.gt_float_int 0000002c 00000000 00000000 000007ec 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 73 .text.gt_float_float 00000018 00000000 00000000 00000818 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 74 .text.ge_int_int 00000010 00000000 00000000 00000830 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 75 .text.ge_int_float 0000001c 00000000 00000000 00000840 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 76 .text.ge_float_int 0000002c 00000000 00000000 0000085c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 77 .text.ge_float_float 00000018 00000000 00000000 00000888 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 78 .text.eq_int_int 00000010 00000000 00000000 000008a0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 79 .text.eq_int_float 0000001c 00000000 00000000 000008b0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 80 .text.eq_float_int 0000002c 00000000 00000000 000008cc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 81 .text.eq_float_float 00000018 00000000 00000000 000008f8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 82 .text.ne_int_int 0000000c 00000000 00000000 00000910 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 83 .text.ne_int_float 0000001c 00000000 00000000 0000091c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 84 .text.ne_float_int 0000002c 00000000 00000000 00000938 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 85 .text.ne_float_float 00000018 00000000 00000000 00000964 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 86 .text.bwand_int_int 00000008 00000000 00000000 0000097c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 87 .text.bwor_int_int 00000008 00000000 00000000 00000984 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 88 .text.bwxor_int_int 00000008 00000000 00000000 0000098c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 89 .text.lshift_int_int 00000008 00000000 00000000 00000994 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 90 .text.rshift_int_int 00000008 00000000 00000000 0000099c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 91 .text.mod_int_int 0000001c 00000000 00000000 000009a4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 92 .text.load_int_reg0_int_int 00000010 00000000 00000000 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CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +109 .text.store_int_reg0_int_float 00000010 00000000 00000000 00000ae0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +110 .text.store_float_reg0_float_int 00000010 00000000 00000000 00000af0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +111 .text.store_float_reg0_float_float 00000010 00000000 00000000 00000b00 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +112 .text.__cosdf 00000060 00000000 00000000 00000b10 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +113 .text.__math_divzerof 00000030 00000000 00000000 00000b70 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +114 .text.__math_invalidf 0000000c 00000000 00000000 00000ba0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +115 .text.__math_oflowf 0000000c 00000000 00000000 00000bac 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +116 .text.__math_uflowf 0000000c 00000000 00000000 00000bb8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +117 .text.__math_xflowf 00000024 00000000 00000000 00000bc4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +118 .text.__rem_pio2_large 00000850 00000000 00000000 00000be8 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +119 .text.__rem_pio2f 00000158 00000000 00000000 00001438 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +120 .text.__sindf 00000058 00000000 00000000 00001590 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +121 .text.__init_ssp 00000054 00000000 00000000 000015e8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +122 .text.__stack_chk_fail 00000008 00000000 00000000 0000163c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +123 .text.__tandf 00000088 00000000 00000000 00001648 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +124 .text.acosf 000001a4 00000000 00000000 000016d0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +125 .text.asinf 00000124 00000000 00000000 00001878 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +126 .text.atan2f 000001dc 00000000 00000000 0000199c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +127 .text.atanf 000001f4 00000000 00000000 00001b78 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +128 .text.cosf 0000018c 00000000 00000000 00001d70 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +129 .text.expf 000000ec 00000000 00000000 00001efc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +130 .text.fabsf 00000008 00000000 00000000 00001fe8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +131 .text.floor 000000a8 00000000 00000000 00001ff0 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +132 .text.floorf 00000094 00000000 00000000 00002098 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +133 .text.logf 000000ec 00000000 00000000 0000212c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +134 .text.powf 000002f0 00000000 00000000 00002218 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +135 .text.scalbn 000000b8 00000000 00000000 00002508 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +136 .text.sinf 000001b0 00000000 00000000 000025c0 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +137 .text.sqrt 00000008 00000000 00000000 00002770 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +138 .text.sqrtf 00000008 00000000 00000000 00002778 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +139 .text.tanf 00000168 00000000 00000000 00002780 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +140 .rodata.PIo2 00000040 00000000 00000000 000028e8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +141 .rodata.ipio2 00000108 00000000 00000000 00002928 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +142 .rodata.init_jk 00000010 00000000 00000000 00002a30 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +143 .rodata.CSWTCH.7 0000000c 00000000 00000000 00002a40 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA +144 .rodata.__exp2f_data 00000148 00000000 00000000 00002a50 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +145 .rodata.__logf_data 00000120 00000000 00000000 00002b98 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +146 .rodata.__powf_log2_data 00000128 00000000 00000000 00002cb8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA +147 .data 00000000 00000000 00000000 00002de0 2**0 + CONTENTS, ALLOC, LOAD, DATA +148 .bss 00000000 00000000 00000000 00002de0 2**0 + ALLOC +149 .bss.__stack_chk_guard 00000004 00000000 00000000 00002de0 2**2 + ALLOC +150 .comment 000004ea 00000000 00000000 00002de0 2**0 + CONTENTS, READONLY +151 .note.GNU-stack 00000000 00000000 00000000 000032ca 2**0 + CONTENTS, READONLY, CODE +152 .debug_aranges 00000040 00000000 00000000 000032d0 2**3 + CONTENTS, RELOC, READONLY, DEBUGGING +153 .debug_info 0000004c 00000000 00000000 00003310 2**0 + CONTENTS, RELOC, READONLY, DEBUGGING +154 .debug_abbrev 00000028 00000000 00000000 0000335c 2**0 + CONTENTS, READONLY, DEBUGGING +155 .debug_line 000000d7 00000000 00000000 00003384 2**0 + CONTENTS, RELOC, READONLY, DEBUGGING +156 .debug_frame 00000020 00000000 00000000 0000345c 2**2 + CONTENTS, RELOC, READONLY, DEBUGGING +157 .debug_str 000000cc 00000000 00000000 0000347c 2**0 + CONTENTS, READONLY, DEBUGGING +158 .ARM.attributes 00000037 00000000 00000000 00003548 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +00000000 l d .text 00000000 .text +00000000 l d .text.auxsub_get_42 00000000 .text.auxsub_get_42 +00000000 l d .text.aux_get_42 00000000 .text.aux_get_42 +00000000 l d .text.entry_function_shell 00000000 .text.entry_function_shell +00000000 l d .text.cast_float_int_int 00000000 .text.cast_float_int_int +00000000 l d .text.cast_float_int_float 00000000 .text.cast_float_int_float +00000000 l d .text.cast_int_float_int 00000000 .text.cast_int_float_int +00000000 l d .text.cast_int_float_float 00000000 .text.cast_int_float_float +00000000 l d .text.get_42_int 00000000 .text.get_42_int +00000000 l d .text.get_42_float 00000000 .text.get_42_float +00000000 l d .text.neg_int 00000000 .text.neg_int +00000000 l d .text.neg_float 00000000 .text.neg_float +00000000 l d .text.sqrt_int 00000000 .text.sqrt_int +00000000 l d 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.text.log_int 00000018 log_int +00000000 g F .text.get_42_float 00000010 get_42_float +00000000 g O .rodata.__logf_data 00000120 .hidden __logf_data +00000000 g F .text.exp_int 00000018 exp_int +00000000 g F .text.powf 000002f0 powf +00000000 g F .text.store_int_reg0_int_float 00000010 store_int_reg0_int_float +00000000 g O .bss.__stack_chk_guard 00000004 __stack_chk_guard +00000000 g F .text.store_float_reg0_float_int 00000010 store_float_reg0_float_int +00000000 g F .text.max_int_int 0000000c max_int_int +00000000 g F .text.__rem_pio2f 00000158 .hidden __rem_pio2f +00000000 g F .text.sign_float 00000020 sign_float +00000000 g F .text.store_int_reg0_int_int 00000010 store_int_reg0_int_int +00000000 g F .text.logf 000000ec logf +00000000 g F .text.sqrt_int 00000038 sqrt_int +00000000 g F .text.floor 000000a8 floor +00000000 g F .text.ge_int_float 0000001c ge_int_float +00000000 g F .text.sqrtf 00000008 sqrtf +00000000 g F .text.load_int_reg1_float_int 00000010 load_int_reg1_float_int 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ge_int_int +00000000 g F .text.__math_xflowf 00000024 .hidden __math_xflowf +00000000 g F .text.__math_invalidf 0000000c .hidden __math_invalidf +00000000 g F .text.fabsf 00000008 fabsf +00000000 g F .text.log_float 00000010 log_float +00000000 g F .text.__stack_chk_fail 00000008 __stack_chk_fail +00000000 g F .text.mul_int_float 00000014 mul_int_float +00000000 g F .text.gt_float_float 00000018 gt_float_float +00000000 g F .text.sub_float_int 00000010 sub_float_int +00000000 g F .text.cosf 0000018c cosf +00000000 g F .text.ne_int_int 0000000c ne_int_int +00000000 g F .text.cast_float_int_int 00000010 cast_float_int_int +00000000 *UND* 00000000 result_float_int +00000000 g F .text.div_int_float 00000014 div_int_float +00000000 g F .text.cast_float_int_float 00000010 cast_float_int_float +00000000 g F .text.sin_float 00000010 sin_float +00000000 g F .text.floordiv_int_int 00000030 floordiv_int_int +00000000 g F .text 00000000 .hidden __aeabi_idiv +00000000 g F .text.tan_float 00000010 tan_float +00000000 g F .text.aux_get_42 0000001c aux_get_42 +00000000 g F .text.store_float_reg0_float_float 00000010 store_float_reg0_float_float +00000000 g F .text.__math_uflowf 0000000c .hidden __math_uflowf +00000000 g F .text.gt_int_int 00000010 gt_int_int +00000000 g F .text.mul_float_float 00000008 mul_float_float +00000000 g F .text.load_int_reg0_int_int 00000010 load_int_reg0_int_int +00000000 g F .text.load_float_reg0_int_int 00000014 load_float_reg0_int_int +00000000 g F .text.pow_int_int 00000030 pow_int_int +00000000 *UND* 00000000 result_int +00000000 g F .text.eq_int_float 0000001c eq_int_float +00000000 g F .text.floordiv_float_float 00000024 floordiv_float_float +00000000 g F .text.exp_float 00000010 exp_float +00000000 g F .text.__cosdf 00000060 .hidden __cosdf +00000000 g F .text.add_int_float 00000014 add_int_float +00000000 g F .text.neg_int 00000008 neg_int +00000000 g F .text.rshift_int_int 00000008 rshift_int_int +00000000 g F .text.lshift_int_int 00000008 lshift_int_int +00000000 g F .text.acos_float 00000010 acos_float +00000000 g F .text.load_float_reg1_int_float 00000010 load_float_reg1_int_float +00000000 g F .text.ne_float_int 0000002c ne_float_int +00000000 g F .text.atan2_int_int 00000030 atan2_int_int +00000000 g F .text.pow_float_float 00000020 pow_float_float +00000000 g F .text.atan2_float_int 00000028 atan2_float_int +00000000 g F .text.div_float_float 00000008 div_float_float +00000000 g F .text.eq_int_int 00000010 eq_int_int +00000000 g F .text.max_float_int 00000018 max_float_int +00000000 g F .text.load_float_reg0_float_float 00000010 load_float_reg0_float_float +00000000 g F .text.__init_ssp 00000054 .hidden __init_ssp +00000148 w F .text 00000004 .hidden __aeabi_ldiv0 +00000000 g F .text.ne_float_float 00000018 ne_float_float +00000000 *UND* 00000000 result_float +00000000 g F .text.min_float_int 00000018 min_float_int +00000000 g F .text.add_int_int 00000008 add_int_int +00000000 g F .text.gt_float_int 0000002c gt_float_int +00000000 g F .text.get_42_int 00000018 get_42_int +00000000 g F .text.sub_int_int 00000008 sub_int_int +00000000 g F .text.asin_float 00000010 asin_float +00000000 g F .text.bwxor_int_int 00000008 bwxor_int_int +00000000 g F .text.max_int_float 0000001c max_int_float +00000000 g F .text 00000128 .hidden __divsi3 +00000000 g F .text.min_int_int 0000000c min_int_int +00000000 g F .text.div_float_int 00000010 div_float_int +00000000 g F .text.acosf 000001a4 acosf +00000000 g F .text.atan2_float_float 00000020 atan2_float_float +00000000 g F .text.gt_int_float 0000001c gt_int_float +00000000 g F .text.min_float_float 00000010 min_float_float +00000000 g F .text.load_int_reg1_int_int 00000010 load_int_reg1_int_int +00000000 g F .text.add_float_float 00000008 add_float_float +00000000 g F .text.floordiv_int_float 0000002c floordiv_int_float +00000000 g F .text.cos_float 00000010 cos_float +00000000 g F .text.max_float_float 00000010 max_float_float +00000000 g F .text.ne_int_float 0000001c ne_int_float +00000000 g F .text.scalbn 000000b8 scalbn +00000000 g F .text.atan2f 000001dc atan2f +00000000 g F .text.entry_function_shell 00000020 entry_function_shell +00000000 g F .text.load_int_reg1_float_float 00000010 load_int_reg1_float_float +00000000 g F .text.load_float_reg0_float_int 00000010 load_float_reg0_float_int +00000000 g F .text.ge_float_int 0000002c ge_float_int +00000000 *UND* 00000000 result_int_int +00000000 g F .text.sin_int 00000018 sin_int +00000000 g F .text.sinf 000001b0 sinf +00000000 g F .text.bwand_int_int 00000008 bwand_int_int +00000000 g F .text.atan_float 00000010 atan_float +00000000 g F .text.eq_float_float 00000018 eq_float_float +00000000 g F .text.eq_float_int 0000002c eq_float_int +00000000 g F .text.tanf 00000168 tanf +00000000 g F .text.load_float_reg1_float_float 00000010 load_float_reg1_float_float +00000000 g F .text.acos_int 00000018 acos_int +00000000 g F .text.ge_float_float 00000018 ge_float_float +00000000 g F .text.__math_divzerof 00000030 .hidden __math_divzerof +00000000 g F .text.asin_int 00000018 asin_int +00000000 g F .text.cast_int_float_float 00000010 cast_int_float_float +00000000 g F .text.mod_int_int 0000001c mod_int_int +00000000 g F .text.atanf 000001f4 atanf +00000148 w F .text 00000004 .hidden __aeabi_idiv0 +00000000 g F .text.load_int_reg1_int_float 00000010 load_int_reg1_int_float +00000000 *UND* 00000000 dummy_int +00000000 *UND* 00000000 result_float_float +00000000 g F .text.expf 000000ec expf +00000000 g F .text.__math_oflowf 0000000c .hidden __math_oflowf +00000000 g F .text.floordiv_float_int 0000002c floordiv_float_int +00000000 g F .text.sign_int 00000014 sign_int +00000000 g F .text.sub_int_float 00000014 sub_int_float +00000000 g F .text.cos_int 00000018 cos_int +00000000 *UND* 00000000 dummy_float +00000000 g F .text.floorf 00000094 floorf +00000000 g F .text.neg_float 00000008 neg_float +00000000 g F .text.abs_int 0000000c abs_int +00000000 g F .text.asinf 00000124 asinf +00000000 g F .text.auxsub_get_42 00000018 auxsub_get_42 +00000000 g O .rodata.__powf_log2_data 00000128 .hidden __powf_log2_data +00000000 g F .text.__sindf 00000058 .hidden __sindf +00000000 g F .text.pow_int_float 0000002c pow_int_float +00000128 g F .text 00000020 .hidden __aeabi_idivmod +00000000 g F .text.load_int_reg0_float_float 00000014 load_int_reg0_float_float +00000000 g F .text.load_int_reg0_float_int 00000014 load_int_reg0_float_int +00000000 g F .text.mul_int_int 00000008 mul_int_int +00000000 g F .text.atan_int 00000018 atan_int +00000000 g F .text.load_float_reg1_float_int 00000010 load_float_reg1_float_int + + + +Disassembly of section .text: + +00000000 <__divsi3>: + 0: e3510000 cmp r1, #0 + 4: 0a000043 beq 118 <.divsi3_skip_div0_test+0x110> + +00000008 <.divsi3_skip_div0_test>: + 8: e020c001 eor ip, r0, r1 + c: 42611000 rsbmi r1, r1, #0 + 10: e2512001 subs r2, r1, #1 + 14: 0a000027 beq b8 <.divsi3_skip_div0_test+0xb0> + 18: e1b03000 movs r3, r0 + 1c: 42603000 rsbmi r3, r0, #0 + 20: e1530001 cmp r3, r1 + 24: 9a000026 bls c4 <.divsi3_skip_div0_test+0xbc> + 28: e1110002 tst r1, r2 + 2c: 0a000028 beq d4 <.divsi3_skip_div0_test+0xcc> + 30: e311020e tst r1, #-536870912 ; 0xe0000000 + 34: 01a01181 lsleq r1, r1, #3 + 38: 03a02008 moveq r2, #8 + 3c: 13a02001 movne r2, #1 + 40: e3510201 cmp r1, #268435456 ; 0x10000000 + 44: 31510003 cmpcc r1, r3 + 48: 31a01201 lslcc r1, r1, #4 + 4c: 31a02202 lslcc r2, r2, #4 + 50: 3afffffa bcc 40 <.divsi3_skip_div0_test+0x38> + 54: e3510102 cmp r1, #-2147483648 ; 0x80000000 + 58: 31510003 cmpcc r1, r3 + 5c: 31a01081 lslcc r1, r1, #1 + 60: 31a02082 lslcc r2, r2, #1 + 64: 3afffffa bcc 54 <.divsi3_skip_div0_test+0x4c> + 68: e3a00000 mov r0, #0 + 6c: e1530001 cmp r3, r1 + 70: 20433001 subcs r3, r3, r1 + 74: 21800002 orrcs r0, r0, r2 + 78: e15300a1 cmp r3, r1, lsr #1 + 7c: 204330a1 subcs r3, r3, r1, lsr #1 + 80: 218000a2 orrcs r0, r0, r2, lsr #1 + 84: e1530121 cmp r3, r1, lsr #2 + 88: 20433121 subcs r3, r3, r1, lsr #2 + 8c: 21800122 orrcs r0, r0, r2, lsr #2 + 90: e15301a1 cmp r3, r1, lsr #3 + 94: 204331a1 subcs r3, r3, r1, lsr #3 + 98: 218001a2 orrcs r0, r0, r2, lsr #3 + 9c: e3530000 cmp r3, #0 + a0: 11b02222 lsrsne r2, r2, #4 + a4: 11a01221 lsrne r1, r1, #4 + a8: 1affffef bne 6c <.divsi3_skip_div0_test+0x64> + ac: e35c0000 cmp ip, #0 + b0: 42600000 rsbmi r0, r0, #0 + b4: e12fff1e bx lr + b4: R_ARM_V4BX *ABS* + b8: e13c0000 teq ip, r0 + bc: 42600000 rsbmi r0, r0, #0 + c0: e12fff1e bx lr + c0: R_ARM_V4BX *ABS* + c4: 33a00000 movcc r0, #0 + c8: 01a00fcc asreq r0, ip, #31 + cc: 03800001 orreq r0, r0, #1 + d0: e12fff1e bx lr + d0: R_ARM_V4BX *ABS* + d4: e3510801 cmp r1, #65536 ; 0x10000 + d8: 21a01821 lsrcs r1, r1, #16 + dc: 23a02010 movcs r2, #16 + e0: 33a02000 movcc r2, #0 + e4: e3510c01 cmp r1, #256 ; 0x100 + e8: 21a01421 lsrcs r1, r1, #8 + ec: 22822008 addcs r2, r2, #8 + f0: e3510010 cmp r1, #16 + f4: 21a01221 lsrcs r1, r1, #4 + f8: 22822004 addcs r2, r2, #4 + fc: e3510004 cmp r1, #4 + 100: 82822003 addhi r2, r2, #3 + 104: 908220a1 addls r2, r2, r1, lsr #1 + 108: e35c0000 cmp ip, #0 + 10c: e1a00233 lsr r0, r3, r2 + 110: 42600000 rsbmi r0, r0, #0 + 114: e12fff1e bx lr + 114: R_ARM_V4BX *ABS* + 118: e3500000 cmp r0, #0 + 11c: c3e00102 mvngt r0, #-2147483648 ; 0x80000000 + 120: b3a00102 movlt r0, #-2147483648 ; 0x80000000 + 124: eafffffe b 148 <__aeabi_idiv0> + 124: R_ARM_JUMP24 __aeabi_idiv0 + +00000128 <__aeabi_idivmod>: + 128: e3510000 cmp r1, #0 + 12c: 0afffff9 beq 118 <.divsi3_skip_div0_test+0x110> + 130: e92d4003 push {r0, r1, lr} + 134: ebffffb3 bl 8 <.divsi3_skip_div0_test> + 138: e8bd4006 pop {r1, r2, lr} + 13c: e0030092 mul r3, r2, r0 + 140: e0411003 sub r1, r1, r3 + 144: e12fff1e bx lr + 144: R_ARM_V4BX *ABS* + +00000148 <__aeabi_idiv0>: + 148: e12fff1e bx lr + 148: R_ARM_V4BX *ABS* + +Disassembly of section .text.auxsub_get_42: + +00000000 : + 0: eef17a04 vmov.f32 s15, #20 ; 0x40a00000 5.0 + 4: ee070a10 vmov s14, r0 + 8: eeb30a05 vmov.f32 s0, #53 ; 0x41a80000 21.0 + c: eeb87ac7 vcvt.f32.s32 s14, s14 + 10: ee070a27 vmla.f32 s0, s14, s15 + 14: e12fff1e bx lr + +Disassembly of section .text.aux_get_42: + +00000000 : + 0: eeb07a08 vmov.f32 s14, #8 ; 0x40400000 3.0 + 4: eddf7a03 vldr s15, [pc, #12] ; 18 + 8: ee407a07 vmla.f32 s15, s0, s14 + c: eefd7ae7 vcvt.s32.f32 s15, s15 + 10: ee170a90 vmov r0, s15 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 auxsub_get_42 + 18: 42280000 .word 0x42280000 + +Disassembly of section .text.entry_function_shell: + +00000000 : + 0: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 4: e24dd084 sub sp, sp, #132 ; 0x84 + 8: e3a00000 mov r0, #0 + c: e5cd0000 strb r0, [sp] + 10: ebfffffe bl 0 + 10: R_ARM_CALL result_int + 14: e3a00001 mov r0, #1 + 18: e28dd084 add sp, sp, #132 ; 0x84 + 1c: e49df004 pop {pc} ; (ldr pc, [sp], #4) + +Disassembly of section .text.cast_float_int_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e1a00001 mov r0, r1 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.cast_float_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.cast_int_float_int: + +00000000 : + 0: eefd7ac0 vcvt.s32.f32 s15, s0 + 4: e1a01000 mov r1, r0 + 8: ee170a90 vmov r0, s15 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.cast_int_float_float: + +00000000 : + 0: eefd7ac0 vcvt.s32.f32 s15, s0 + 4: eeb00a60 vmov.f32 s0, s1 + 8: ee170a90 vmov r0, s15 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.get_42_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL aux_get_42 + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.get_42_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL aux_get_42 + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.neg_int: + +00000000 : + 0: e2600000 rsb r0, r0, #0 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int + +Disassembly of section .text.neg_float: + +00000000 : + 0: eeb10a40 vneg.f32 s0, s0 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_float + +Disassembly of section .text.sqrt_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ed2d8b02 vpush {d8} + 10: eeb50a40 vcmp.f32 s0, #0.0 + 14: eeb18ac0 vsqrt.f32 s16, s0 + 18: eef1fa10 vmrs APSR_nzcv, fpscr + 1c: 4a000003 bmi 30 + 20: eeb00a48 vmov.f32 s0, s16 + 24: ecbd8b02 vpop {d8} + 28: e8bd4010 pop {r4, lr} + 2c: eafffffe b 0 + 2c: R_ARM_JUMP24 result_float + 30: ebfffffe bl 0 + 30: R_ARM_CALL sqrtf + 34: eafffff9 b 20 + +Disassembly of section .text.sqrt_float: + +00000000 : + 0: eeb50a40 vcmp.f32 s0, #0.0 + 4: e92d4010 push {r4, lr} + 8: ed2d8b02 vpush {d8} + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: eeb18ac0 vsqrt.f32 s16, s0 + 14: 4a000003 bmi 28 + 18: eeb00a48 vmov.f32 s0, s16 + 1c: ecbd8b02 vpop {d8} + 20: e8bd4010 pop {r4, lr} + 24: eafffffe b 0 + 24: R_ARM_JUMP24 result_float + 28: ebfffffe bl 0 + 28: R_ARM_CALL sqrtf + 2c: eafffff9 b 18 + +Disassembly of section .text.exp_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL expf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.exp_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL expf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.log_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL logf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.log_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL logf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.sin_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL sinf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.sin_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL sinf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.cos_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL cosf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.cos_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL cosf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.tan_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL tanf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.tan_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL tanf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.asin_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL asinf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.asin_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL asinf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.acos_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL acosf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.acos_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL acosf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.atan_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ebfffffe bl 0 + c: R_ARM_CALL atanf + 10: e8bd4010 pop {r4, lr} + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float + +Disassembly of section .text.atan_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ebfffffe bl 0 + 4: R_ARM_CALL atanf + 8: e8bd4010 pop {r4, lr} + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float + +Disassembly of section .text.abs_float: + +00000000 : + 0: eeb00ac0 vabs.f32 s0, s0 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_float + +Disassembly of section .text.abs_int: + +00000000 : + 0: e3500000 cmp r0, #0 + 4: b2600000 rsblt r0, r0, #0 + 8: eafffffe b 0 + 8: R_ARM_JUMP24 result_int + +Disassembly of section .text.sign_int: + +00000000 : + 0: e1a03fa0 lsr r3, r0, #31 + 4: e3500000 cmp r0, #0 + 8: d2630000 rsble r0, r3, #0 + c: c2630001 rsbgt r0, r3, #1 + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_int + +Disassembly of section .text.sign_float: + +00000000 : + 0: eeb50ac0 vcmpe.f32 s0, #0.0 + 4: eef1fa10 vmrs APSR_nzcv, fpscr + 8: c3a00001 movgt r0, #1 + c: d3a00000 movle r0, #0 + 10: 43a03001 movmi r3, #1 + 14: 53a03000 movpl r3, #0 + 18: e0400003 sub r0, r0, r3 + 1c: eafffffe b 0 + 1c: R_ARM_JUMP24 result_int + +Disassembly of section .text.atan2_int_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ee071a90 vmov s15, r1 + 10: e24dd00c sub sp, sp, #12 + 14: e58d1004 str r1, [sp, #4] + 18: eef80ae7 vcvt.f32.s32 s1, s15 + 1c: ebfffffe bl 0 + 1c: R_ARM_CALL atan2f + 20: e59d0004 ldr r0, [sp, #4] + 24: e28dd00c add sp, sp, #12 + 28: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 2c: eafffffe b 0 + 2c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.atan2_int_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ee070a90 vmov s15, r0 + 8: ed2d8b02 vpush {d8} + c: eeb08a40 vmov.f32 s16, s0 + 10: eeb80ae7 vcvt.f32.s32 s0, s15 + 14: eef00a48 vmov.f32 s1, s16 + 18: ebfffffe bl 0 + 18: R_ARM_CALL atan2f + 1c: eef00a48 vmov.f32 s1, s16 + 20: ecbd8b02 vpop {d8} + 24: e8bd4010 pop {r4, lr} + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.atan2_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e24dd00c sub sp, sp, #12 + c: eef80ae7 vcvt.f32.s32 s1, s15 + 10: e58d0004 str r0, [sp, #4] + 14: ebfffffe bl 0 + 14: R_ARM_CALL atan2f + 18: e59d0004 ldr r0, [sp, #4] + 1c: e28dd00c add sp, sp, #12 + 20: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 24: eafffffe b 0 + 24: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.atan2_float_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ed2d8b02 vpush {d8} + 8: eeb08a60 vmov.f32 s16, s1 + c: ebfffffe bl 0 + c: R_ARM_CALL atan2f + 10: eef00a48 vmov.f32 s1, s16 + 14: ecbd8b02 vpop {d8} + 18: e8bd4010 pop {r4, lr} + 1c: eafffffe b 0 + 1c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.pow_int_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ee071a90 vmov s15, r1 + 10: e24dd00c sub sp, sp, #12 + 14: e58d1004 str r1, [sp, #4] + 18: eef80ae7 vcvt.f32.s32 s1, s15 + 1c: ebfffffe bl 0 + 1c: R_ARM_CALL powf + 20: e59d0004 ldr r0, [sp, #4] + 24: e28dd00c add sp, sp, #12 + 28: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 2c: eafffffe b 0 + 2c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.pow_int_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ee070a90 vmov s15, r0 + 8: ed2d8b02 vpush {d8} + c: eeb08a40 vmov.f32 s16, s0 + 10: eeb80ae7 vcvt.f32.s32 s0, s15 + 14: eef00a48 vmov.f32 s1, s16 + 18: ebfffffe bl 0 + 18: R_ARM_CALL powf + 1c: eef00a48 vmov.f32 s1, s16 + 20: ecbd8b02 vpop {d8} + 24: e8bd4010 pop {r4, lr} + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.pow_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e24dd00c sub sp, sp, #12 + c: eef80ae7 vcvt.f32.s32 s1, s15 + 10: e58d0004 str r0, [sp, #4] + 14: ebfffffe bl 0 + 14: R_ARM_CALL powf + 18: e59d0004 ldr r0, [sp, #4] + 1c: e28dd00c add sp, sp, #12 + 20: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 24: eafffffe b 0 + 24: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.pow_float_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ed2d8b02 vpush {d8} + 8: eeb08a60 vmov.f32 s16, s1 + c: ebfffffe bl 0 + c: R_ARM_CALL powf + 10: eef00a48 vmov.f32 s1, s16 + 14: ecbd8b02 vpop {d8} + 18: e8bd4010 pop {r4, lr} + 1c: eafffffe b 0 + 1c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.min_int_int: + +00000000 : + 0: e1510000 cmp r1, r0 + 4: b1a00001 movlt r0, r1 + 8: eafffffe b 0 + 8: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.max_int_int: + +00000000 : + 0: e1510000 cmp r1, r0 + 4: a1a00001 movge r0, r1 + 8: eafffffe b 0 + 8: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.min_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: eeb40ae0 vcmpe.f32 s0, s1 + 10: eef1fa10 vmrs APSR_nzcv, fpscr + 14: 5eb00a60 vmovpl.f32 s0, s1 + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.max_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: eeb40ae0 vcmpe.f32 s0, s1 + 10: eef1fa10 vmrs APSR_nzcv, fpscr + 14: deb00a60 vmovle.f32 s0, s1 + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.min_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: eeb40ae7 vcmpe.f32 s0, s15 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: 5eb00a67 vmovpl.f32 s0, s15 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.max_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: eeb40ae7 vcmpe.f32 s0, s15 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: deb00a67 vmovle.f32 s0, s15 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.min_float_float: + +00000000 : + 0: eeb40ae0 vcmpe.f32 s0, s1 + 4: eef1fa10 vmrs APSR_nzcv, fpscr + 8: 5eb00a60 vmovpl.f32 s0, s1 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.max_float_float: + +00000000 : + 0: eeb40ae0 vcmpe.f32 s0, s1 + 4: eef1fa10 vmrs APSR_nzcv, fpscr + 8: deb00a60 vmovle.f32 s0, s1 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.add_int_int: + +00000000 : + 0: e0800001 add r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.add_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ee300a20 vadd.f32 s0, s0, s1 + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.add_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: ee370a80 vadd.f32 s0, s15, s0 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.add_float_float: + +00000000 : + 0: ee300a20 vadd.f32 s0, s0, s1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.sub_int_int: + +00000000 : + 0: e0400001 sub r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.sub_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ee300a60 vsub.f32 s0, s0, s1 + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.sub_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: ee300a67 vsub.f32 s0, s0, s15 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.sub_float_float: + +00000000 : + 0: ee300a60 vsub.f32 s0, s0, s1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.mul_int_int: + +00000000 : + 0: e0000091 mul r0, r1, r0 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.mul_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ee200a20 vmul.f32 s0, s0, s1 + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.mul_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: ee270a80 vmul.f32 s0, s15, s0 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.mul_float_float: + +00000000 : + 0: ee200a20 vmul.f32 s0, s0, s1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.div_int_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e24dd008 sub sp, sp, #8 + 8: e1a00001 mov r0, r1 + c: eeb80ae7 vcvt.f32.s32 s0, s15 + 10: e58d1004 str r1, [sp, #4] + 14: ee071a90 vmov s15, r1 + 18: eef87ae7 vcvt.f32.s32 s15, s15 + 1c: ee800a27 vdiv.f32 s0, s0, s15 + 20: e28dd008 add sp, sp, #8 + 24: eafffffe b 0 + 24: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.div_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef00a40 vmov.f32 s1, s0 + 8: eeb80ae7 vcvt.f32.s32 s0, s15 + c: ee800a20 vdiv.f32 s0, s0, s1 + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.div_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: ee800a27 vdiv.f32 s0, s0, s15 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.div_float_float: + +00000000 : + 0: ee800a20 vdiv.f32 s0, s0, s1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.floordiv_int_int: + +00000000 : + 0: e92d4070 push {r4, r5, r6, lr} + 4: e1a05000 mov r5, r0 + 8: e1a04001 mov r4, r1 + c: ebfffffe bl 128 <__aeabi_idivmod> + c: R_ARM_CALL __aeabi_idivmod + 10: e3510000 cmp r1, #0 + 14: 0a000002 beq 24 + 18: e1a03fa4 lsr r3, r4, #31 + 1c: e1530fa5 cmp r3, r5, lsr #31 + 20: 12400001 subne r0, r0, #1 + 24: e1a01004 mov r1, r4 + 28: e8bd4070 pop {r4, r5, r6, lr} + 2c: eafffffe b 0 + 2c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.floordiv_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e92d4010 push {r4, lr} + 8: ed2d8b02 vpush {d8} + c: eeb08a40 vmov.f32 s16, s0 + 10: eeb80ae7 vcvt.f32.s32 s0, s15 + 14: ee800a08 vdiv.f32 s0, s0, s16 + 18: ebfffffe bl 0 + 18: R_ARM_CALL floorf + 1c: eef00a48 vmov.f32 s1, s16 + 20: ecbd8b02 vpop {d8} + 24: e8bd4010 pop {r4, lr} + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.floordiv_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: eef87ae7 vcvt.f32.s32 s15, s15 + c: e24dd00c sub sp, sp, #12 + 10: e58d0004 str r0, [sp, #4] + 14: ee800a27 vdiv.f32 s0, s0, s15 + 18: ebfffffe bl 0 + 18: R_ARM_CALL floorf + 1c: e59d0004 ldr r0, [sp, #4] + 20: e28dd00c add sp, sp, #12 + 24: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.floordiv_float_float: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ee800a20 vdiv.f32 s0, s0, s1 + 8: ed2d8b02 vpush {d8} + c: eeb08a60 vmov.f32 s16, s1 + 10: ebfffffe bl 0 + 10: R_ARM_CALL floorf + 14: eef00a48 vmov.f32 s1, s16 + 18: ecbd8b02 vpop {d8} + 1c: e8bd4010 pop {r4, lr} + 20: eafffffe b 0 + 20: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.gt_int_int: + +00000000 : + 0: e1500001 cmp r0, r1 + 4: d3a00000 movle r0, #0 + 8: c3a00001 movgt r0, #1 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.gt_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: eef47ac0 vcmpe.f32 s15, s0 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: c3a00001 movgt r0, #1 + 14: d3a00000 movle r0, #0 + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.gt_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e24dd008 sub sp, sp, #8 + 8: e1a01000 mov r1, r0 + c: eef87ae7 vcvt.f32.s32 s15, s15 + 10: e58d0004 str r0, [sp, #4] + 14: eef47ac0 vcmpe.f32 s15, s0 + 18: eef1fa10 vmrs APSR_nzcv, fpscr + 1c: 43a00001 movmi r0, #1 + 20: 53a00000 movpl r0, #0 + 24: e28dd008 add sp, sp, #8 + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.gt_float_float: + +00000000 : + 0: eeb40ae0 vcmpe.f32 s0, s1 + 4: eeb00a60 vmov.f32 s0, s1 + 8: eef1fa10 vmrs APSR_nzcv, fpscr + c: c3a00001 movgt r0, #1 + 10: d3a00000 movle r0, #0 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.ge_int_int: + +00000000 : + 0: e1500001 cmp r0, r1 + 4: b3a00000 movlt r0, #0 + 8: a3a00001 movge r0, #1 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.ge_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: eef47ac0 vcmpe.f32 s15, s0 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: a3a00001 movge r0, #1 + 14: b3a00000 movlt r0, #0 + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.ge_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e24dd008 sub sp, sp, #8 + 8: e1a01000 mov r1, r0 + c: eef87ae7 vcvt.f32.s32 s15, s15 + 10: e58d0004 str r0, [sp, #4] + 14: eef47ac0 vcmpe.f32 s15, s0 + 18: eef1fa10 vmrs APSR_nzcv, fpscr + 1c: 93a00001 movls r0, #1 + 20: 83a00000 movhi r0, #0 + 24: e28dd008 add sp, sp, #8 + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.ge_float_float: + +00000000 : + 0: eeb40ae0 vcmpe.f32 s0, s1 + 4: eeb00a60 vmov.f32 s0, s1 + 8: eef1fa10 vmrs APSR_nzcv, fpscr + c: a3a00001 movge r0, #1 + 10: b3a00000 movlt r0, #0 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.eq_int_int: + +00000000 : + 0: e0400001 sub r0, r0, r1 + 4: e16f0f10 clz r0, r0 + 8: e1a002a0 lsr r0, r0, #5 + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.eq_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: eef47a40 vcmp.f32 s15, s0 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: 03a00001 moveq r0, #1 + 14: 13a00000 movne r0, #0 + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.eq_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e24dd008 sub sp, sp, #8 + 8: e1a01000 mov r1, r0 + c: eef87ae7 vcvt.f32.s32 s15, s15 + 10: e58d0004 str r0, [sp, #4] + 14: eef47a40 vcmp.f32 s15, s0 + 18: eef1fa10 vmrs APSR_nzcv, fpscr + 1c: 03a00001 moveq r0, #1 + 20: 13a00000 movne r0, #0 + 24: e28dd008 add sp, sp, #8 + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.eq_float_float: + +00000000 : + 0: eeb40a60 vcmp.f32 s0, s1 + 4: eeb00a60 vmov.f32 s0, s1 + 8: eef1fa10 vmrs APSR_nzcv, fpscr + c: 03a00001 moveq r0, #1 + 10: 13a00000 movne r0, #0 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.ne_int_int: + +00000000 : + 0: e0500001 subs r0, r0, r1 + 4: 13a00001 movne r0, #1 + 8: eafffffe b 0 + 8: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.ne_int_float: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: eef87ae7 vcvt.f32.s32 s15, s15 + 8: eef47a40 vcmp.f32 s15, s0 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: 13a00001 movne r0, #1 + 14: 03a00000 moveq r0, #0 + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.ne_float_int: + +00000000 : + 0: ee070a90 vmov s15, r0 + 4: e24dd008 sub sp, sp, #8 + 8: e1a01000 mov r1, r0 + c: eef87ae7 vcvt.f32.s32 s15, s15 + 10: e58d0004 str r0, [sp, #4] + 14: eef47a40 vcmp.f32 s15, s0 + 18: eef1fa10 vmrs APSR_nzcv, fpscr + 1c: 13a00001 movne r0, #1 + 20: 03a00000 moveq r0, #0 + 24: e28dd008 add sp, sp, #8 + 28: eafffffe b 0 + 28: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.ne_float_float: + +00000000 : + 0: eeb40a60 vcmp.f32 s0, s1 + 4: eeb00a60 vmov.f32 s0, s1 + 8: eef1fa10 vmrs APSR_nzcv, fpscr + c: 13a00001 movne r0, #1 + 10: 03a00000 moveq r0, #0 + 14: eafffffe b 0 + 14: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.bwand_int_int: + +00000000 : + 0: e0000001 and r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.bwor_int_int: + +00000000 : + 0: e1800001 orr r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.bwxor_int_int: + +00000000 : + 0: e0200001 eor r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.lshift_int_int: + +00000000 : + 0: e1a00110 lsl r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.rshift_int_int: + +00000000 : + 0: e1a00150 asr r0, r0, r1 + 4: eafffffe b 0 + 4: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.mod_int_int: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: e1a04001 mov r4, r1 + 8: ebfffffe bl 128 <__aeabi_idivmod> + 8: R_ARM_CALL __aeabi_idivmod + c: e1a00001 mov r0, r1 + 10: e1a01004 mov r1, r4 + 14: e8bd4010 pop {r4, lr} + 18: eafffffe b 0 + 18: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.load_int_reg0_int_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5930000 ldr r0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.load_int_reg1_int_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5931000 ldr r1, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.load_float_reg0_int_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: e1a00001 mov r0, r1 + c: ed930a00 vldr s0, [r3] + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.load_float_reg1_int_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: ed930a00 vldr s0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.load_int_reg0_int_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5930000 ldr r0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.load_int_reg1_int_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5931000 ldr r1, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.load_float_reg0_int_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: eef00a40 vmov.f32 s1, s0 + c: ed930a00 vldr s0, [r3] + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.load_float_reg1_int_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: ed930a00 vldr s0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.load_int_reg0_float_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e1a01000 mov r1, r0 + c: e5930000 ldr r0, [r3] + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.load_int_reg1_float_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5930000 ldr r0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.load_float_reg0_float_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: ed930a00 vldr s0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.load_float_reg1_float_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: edd30a00 vldr s1, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.load_int_reg0_float_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: eeb00a60 vmov.f32 s0, s1 + c: e5930000 ldr r0, [r3] + 10: eafffffe b 0 + 10: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.load_int_reg1_float_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5930000 ldr r0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.load_float_reg0_float_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: ed930a00 vldr s0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.load_float_reg1_float_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: edd30a00 vldr s1, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.store_int_reg0_int_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5830000 str r0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_int + +Disassembly of section .text.store_int_reg0_int_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_int + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_int + 8: e5830000 str r0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_int_float + +Disassembly of section .text.store_float_reg0_float_int: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: ed830a00 vstr s0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_int + +Disassembly of section .text.store_float_reg0_float_float: + +00000000 : + 0: e3003000 movw r3, #0 + 0: R_ARM_MOVW_ABS_NC dummy_float + 4: e3403000 movt r3, #0 + 4: R_ARM_MOVT_ABS dummy_float + 8: ed830a00 vstr s0, [r3] + c: eafffffe b 0 + c: R_ARM_JUMP24 result_float_float + +Disassembly of section .text.__cosdf: + +00000000 <__cosdf>: + 0: ee600b00 vmul.f64 d16, d0, d0 + 4: eddf6b0d vldr d22, [pc, #52] ; 40 <__cosdf+0x40> + 8: eef71b00 vmov.f64 d17, #112 ; 0x3f800000 1.0 + c: eddf5b0d vldr d21, [pc, #52] ; 48 <__cosdf+0x48> + 10: eddf2b0e vldr d18, [pc, #56] ; 50 <__cosdf+0x50> + 14: eddf4b0f vldr d20, [pc, #60] ; 58 <__cosdf+0x58> + 18: ee401ba6 vmla.f64 d17, d16, d22 + 1c: ee603ba0 vmul.f64 d19, d16, d16 + 20: ee502ba5 vnmls.f64 d18, d16, d21 + 24: ee600ba3 vmul.f64 d16, d16, d19 + 28: eeb00b61 vmov.f64 d0, d17 + 2c: ee030ba4 vmla.f64 d0, d19, d20 + 30: ee020ba0 vmla.f64 d0, d18, d16 + 34: eeb70bc0 vcvt.f32.f64 s0, d0 + 38: e12fff1e bx lr + 3c: e320f000 nop {0} + 40: fd0c5e81 .word 0xfd0c5e81 + 44: bfdfffff .word 0xbfdfffff + 48: e0ee5069 .word 0xe0ee5069 + 4c: 3ef99342 .word 0x3ef99342 + 50: e80f1e27 .word 0xe80f1e27 + 54: 3f56c087 .word 0x3f56c087 + 58: e1053a42 .word 0xe1053a42 + 5c: 3fa55553 .word 0x3fa55553 + +Disassembly of section .text.__math_divzerof: + +00000000 <__math_divzerof>: + 0: e3500000 cmp r0, #0 + 4: eeff6a00 vmov.f32 s13, #240 ; 0xbf800000 -1.0 + 8: eef77a00 vmov.f32 s15, #112 ; 0x3f800000 1.0 + c: e24dd008 sub sp, sp, #8 + 10: ed9f7a05 vldr s14, [pc, #20] ; 2c <__math_divzerof+0x2c> + 14: 1ef07a66 vmovne.f32 s15, s13 + 18: edcd7a01 vstr s15, [sp, #4] + 1c: ed9d0a01 vldr s0, [sp, #4] + 20: ee800a07 vdiv.f32 s0, s0, s14 + 24: e28dd008 add sp, sp, #8 + 28: e12fff1e bx lr + 2c: 00000000 .word 0x00000000 + +Disassembly of section .text.__math_invalidf: + +00000000 <__math_invalidf>: + 0: ee300a40 vsub.f32 s0, s0, s0 + 4: ee800a00 vdiv.f32 s0, s0, s0 + 8: e12fff1e bx lr + +Disassembly of section .text.__math_oflowf: + +00000000 <__math_oflowf>: + 0: ed9f0a00 vldr s0, [pc] ; 8 <__math_oflowf+0x8> + 4: eafffffe b 0 <__math_oflowf> + 4: R_ARM_JUMP24 __math_xflowf + 8: 70000000 .word 0x70000000 + +Disassembly of section .text.__math_uflowf: + +00000000 <__math_uflowf>: + 0: ed9f0a00 vldr s0, [pc] ; 8 <__math_uflowf+0x8> + 4: eafffffe b 0 <__math_uflowf> + 4: R_ARM_JUMP24 __math_xflowf + 8: 10000000 .word 0x10000000 + +Disassembly of section .text.__math_xflowf: + +00000000 <__math_xflowf>: + 0: e3500000 cmp r0, #0 + 4: e24dd008 sub sp, sp, #8 + 8: 1ef17a40 vnegne.f32 s15, s0 + c: 0ef07a40 vmoveq.f32 s15, s0 + 10: edcd7a01 vstr s15, [sp, #4] + 14: eddd7a01 vldr s15, [sp, #4] + 18: ee200a27 vmul.f32 s0, s0, s15 + 1c: e28dd008 add sp, sp, #8 + 20: e12fff1e bx lr + +Disassembly of section .text.__rem_pio2_large: + +00000000 <__rem_pio2_large>: + 0: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 4: e1a0c003 mov ip, r3 + 8: e1a0a002 mov sl, r2 + c: ed2d8b04 vpush {d8-d9} + 10: e24ddf93 sub sp, sp, #588 ; 0x24c + 14: e3720014 cmn r2, #20 + 18: e3002000 movw r2, #0 + 18: R_ARM_MOVW_ABS_NC init_jk + 1c: e3402000 movt r2, #0 + 1c: R_ARM_MOVT_ABS init_jk + 20: e1a09000 mov r9, r0 + 24: e58d3008 str r3, [sp, #8] + 28: e1a03001 mov r3, r1 + 2c: e59d1280 ldr r1, [sp, #640] ; 0x280 + 30: e24c8001 sub r8, ip, #1 + 34: e7925101 ldr r5, [r2, r1, lsl #2] + 38: ba000189 blt 664 <__rem_pio2_large+0x664> + 3c: e24a2003 sub r2, sl, #3 + 40: e30a1aab movw r1, #43691 ; 0xaaab + 44: e3421aaa movt r1, #10922 ; 0x2aaa + 48: e0c10291 smull r0, r1, r1, r2 + 4c: e1a02fc2 asr r2, r2, #31 + 50: e0622141 rsb r2, r2, r1, asr #2 + 54: e58d2004 str r2, [sp, #4] + 58: e1a01002 mov r1, r2 + 5c: e3e02017 mvn r2, #23 + 60: e0222291 mla r2, r1, r2, r2 + 64: e08aa002 add sl, sl, r2 + 68: e59d2004 ldr r2, [sp, #4] + 6c: e0950008 adds r0, r5, r8 + 70: e0422008 sub r2, r2, r8 + 74: 4a00000e bmi b4 <__rem_pio2_large+0xb4> + 78: e2800001 add r0, r0, #1 + 7c: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 80: e300c000 movw ip, #0 + 80: R_ARM_MOVW_ABS_NC ipio2 + 84: e340c000 movt ip, #0 + 84: R_ARM_MOVT_ABS ipio2 + 88: e0800002 add r0, r0, r2 + 8c: e28d1068 add r1, sp, #104 ; 0x68 + 90: e3520000 cmp r2, #0 + 94: eef00b61 vmov.f64 d16, d17 + 98: a79ce102 ldrge lr, [ip, r2, lsl #2] + 9c: e2822001 add r2, r2, #1 + a0: ae07ea90 vmovge s15, lr + a4: aef80be7 vcvtge.f64.s32 d16, s15 + a8: e1520000 cmp r2, r0 + ac: ece10b02 vstmia r1!, {d16} + b0: 1afffff6 bne 90 <__rem_pio2_large+0x90> + b4: e59d2008 ldr r2, [sp, #8] + b8: e3550000 cmp r5, #0 + bc: e1a04182 lsl r4, r2, #3 + c0: ba00000d blt fc <__rem_pio2_large+0xfc> + c4: e28d0068 add r0, sp, #104 ; 0x68 + c8: f2c00e30 vmov.i64 d16, #0x0000000000000000 + cc: e0800004 add r0, r0, r4 + d0: e28def6a add lr, sp, #424 ; 0x1a8 + d4: e1a0c008 mov ip, r8 + d8: e0856002 add r6, r5, r2 + dc: e0891004 add r1, r9, r4 + e0: e3580000 cmp r8, #0 + e4: aa000081 bge 2f0 <__rem_pio2_large+0x2f0> + e8: e28cc001 add ip, ip, #1 + ec: e2800008 add r0, r0, #8 + f0: e15c0006 cmp ip, r6 + f4: ecee0b02 vstmia lr!, {d16} + f8: 1afffff8 bne e0 <__rem_pio2_large+0xe0> + fc: e2452001 sub r2, r5, #1 + 100: e28d1f92 add r1, sp, #584 ; 0x248 + 104: e1a06105 lsl r6, r5, #2 + 108: e28d7018 add r7, sp, #24 + 10c: e0811102 add r1, r1, r2, lsl #2 + 110: e1a0b005 mov fp, r5 + 114: e2462004 sub r2, r6, #4 + 118: e58d5000 str r5, [sp] + 11c: e0894004 add r4, r9, r4 + 120: e0876006 add r6, r7, r6 + 124: e1a05001 mov r5, r1 + 128: e0872002 add r2, r7, r2 + 12c: e58d3010 str r3, [sp, #16] + 130: e58d200c str r2, [sp, #12] + 134: e1a0318b lsl r3, fp, #3 + 138: e35b0000 cmp fp, #0 + 13c: e08d2003 add r2, sp, r3 + 140: ed920b6a vldr d0, [r2, #424] ; 0x1a8 + 144: da00000f ble 188 <__rem_pio2_large+0x188> + 148: e28d1f6a add r1, sp, #424 ; 0x1a8 + 14c: eddf4bf1 vldr d20, [pc, #964] ; 518 <__rem_pio2_large+0x518> + 150: eddf3bf2 vldr d19, [pc, #968] ; 520 <__rem_pio2_large+0x520> + 154: e0813003 add r3, r1, r3 + 158: e1a02007 mov r2, r7 + 15c: ee600b24 vmul.f64 d16, d0, d20 + 160: eef01b40 vmov.f64 d17, d0 + 164: ed732b02 vldmdb r3!, {d18} + 168: eefd7be0 vcvt.s32.f64 s15, d16 + 16c: e1530001 cmp r3, r1 + 170: eef80be7 vcvt.f64.s32 d16, s15 + 174: ee401be3 vmls.f64 d17, d16, d19 + 178: ee300ba2 vadd.f64 d0, d16, d18 + 17c: eefd7be1 vcvt.s32.f64 s15, d17 + 180: ece27a01 vstmia r2!, {s15} + 184: 1afffff4 bne 15c <__rem_pio2_large+0x15c> + 188: e1a0000a mov r0, sl + 18c: ebfffffe bl 0 <__rem_pio2_large> + 18c: R_ARM_CALL scalbn + 190: eef40b00 vmov.f64 d16, #64 ; 0x3e000000 0.125 + 194: eeb08b40 vmov.f64 d8, d0 + 198: ee200b20 vmul.f64 d0, d0, d16 + 19c: ebfffffe bl 0 <__rem_pio2_large> + 19c: R_ARM_CALL floor + 1a0: eef20b00 vmov.f64 d16, #32 ; 0x41000000 8.0 + 1a4: e35a0000 cmp sl, #0 + 1a8: ee008b60 vmls.f64 d8, d0, d16 + 1ac: eebd9bc8 vcvt.s32.f64 s18, d8 + 1b0: eef80bc9 vcvt.f64.s32 d16, s18 + 1b4: ee388b60 vsub.f64 d8, d8, d16 + 1b8: da000055 ble 314 <__rem_pio2_large+0x314> + 1bc: e24b1001 sub r1, fp, #1 + 1c0: e28d3f92 add r3, sp, #584 ; 0x248 + 1c4: e26a2017 rsb r2, sl, #23 + 1c8: e0831101 add r1, r3, r1, lsl #2 + 1cc: e26a3018 rsb r3, sl, #24 + 1d0: e511c230 ldr ip, [r1, #-560] ; 0xfffffdd0 + 1d4: e1a0035c asr r0, ip, r3 + 1d8: e04c3310 sub r3, ip, r0, lsl r3 + 1dc: ee19ca10 vmov ip, s18 + 1e0: e5013230 str r3, [r1, #-560] ; 0xfffffdd0 + 1e4: e1a02253 asr r2, r3, r2 + 1e8: e3520000 cmp r2, #0 + 1ec: e08c0000 add r0, ip, r0 + 1f0: ee090a10 vmov s18, r0 + 1f4: ca0000f3 bgt 5c8 <__rem_pio2_large+0x5c8> + 1f8: eeb58b40 vcmp.f64 d8, #0.0 + 1fc: eef1fa10 vmrs APSR_nzcv, fpscr + 200: 1a000087 bne 424 <__rem_pio2_large+0x424> + 204: e59d3000 ldr r3, [sp] + 208: e15b0003 cmp fp, r3 + 20c: da000007 ble 230 <__rem_pio2_large+0x230> + 210: e087310b add r3, r7, fp, lsl #2 + 214: e3a01000 mov r1, #0 + 218: e5330004 ldr r0, [r3, #-4]! + 21c: e1811000 orr r1, r1, r0 + 220: e1530006 cmp r3, r6 + 224: 1afffffb bne 218 <__rem_pio2_large+0x218> + 228: e3510000 cmp r1, #0 + 22c: 1a0000f5 bne 608 <__rem_pio2_large+0x608> + 230: e5153230 ldr r3, [r5, #-560] ; 0xfffffdd0 + 234: e28b2001 add r2, fp, #1 + 238: e1a0e002 mov lr, r2 + 23c: e3530000 cmp r3, #0 + 240: 1a0000ee bne 600 <__rem_pio2_large+0x600> + 244: e59d300c ldr r3, [sp, #12] + 248: e3a01001 mov r1, #1 + 24c: e5330004 ldr r0, [r3, #-4]! + 250: e2811001 add r1, r1, #1 + 254: e3500000 cmp r0, #0 + 258: 0afffffb beq 24c <__rem_pio2_large+0x24c> + 25c: e08b1001 add r1, fp, r1 + 260: e59d0008 ldr r0, [sp, #8] + 264: e28dc068 add ip, sp, #104 ; 0x68 + 268: e59d3004 ldr r3, [sp, #4] + 26c: e083300b add r3, r3, fp + 270: e080b00b add fp, r0, fp + 274: e3000000 movw r0, #0 + 274: R_ARM_MOVW_ABS_NC ipio2 + 278: e3400000 movt r0, #0 + 278: R_ARM_MOVT_ABS ipio2 + 27c: e08cc18b add ip, ip, fp, lsl #3 + 280: e28dbf6a add fp, sp, #424 ; 0x1a8 + 284: e08bb182 add fp, fp, r2, lsl #3 + 288: e0800103 add r0, r0, r3, lsl #2 + 28c: e5b03004 ldr r3, [r0, #4]! + 290: e3580000 cmp r8, #0 + 294: ee073a90 vmov s15, r3 + 298: eef80be7 vcvt.f64.s32 d16, s15 + 29c: ecec0b02 vstmia ip!, {d16} + 2a0: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 2a4: ba000006 blt 2c4 <__rem_pio2_large+0x2c4> + 2a8: e1a0200c mov r2, ip + 2ac: e1a03009 mov r3, r9 + 2b0: ecf32b02 vldmia r3!, {d18} + 2b4: ed721b02 vldmdb r2!, {d17} + 2b8: e1530004 cmp r3, r4 + 2bc: ee420ba1 vmla.f64 d16, d18, d17 + 2c0: 1afffffa bne 2b0 <__rem_pio2_large+0x2b0> + 2c4: e28ee001 add lr, lr, #1 + 2c8: eceb0b02 vstmia fp!, {d16} + 2cc: e15e0001 cmp lr, r1 + 2d0: daffffed ble 28c <__rem_pio2_large+0x28c> + 2d4: e1a0b001 mov fp, r1 + 2d8: eaffff95 b 134 <__rem_pio2_large+0x134> + 2dc: e28cc001 add ip, ip, #1 + 2e0: e2800008 add r0, r0, #8 + 2e4: e15c0006 cmp ip, r6 + 2e8: ecee0b02 vstmia lr!, {d16} + 2ec: 0affff82 beq fc <__rem_pio2_large+0xfc> + 2f0: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 2f4: e1a07000 mov r7, r0 + 2f8: e1a02009 mov r2, r9 + 2fc: ecf22b02 vldmia r2!, {d18} + 300: ed771b02 vldmdb r7!, {d17} + 304: e1520001 cmp r2, r1 + 308: ee420ba1 vmla.f64 d16, d18, d17 + 30c: 1afffffa bne 2fc <__rem_pio2_large+0x2fc> + 310: eafffff1 b 2dc <__rem_pio2_large+0x2dc> + 314: 0a00000e beq 354 <__rem_pio2_large+0x354> + 318: eef60b00 vmov.f64 d16, #96 ; 0x3f000000 0.5 + 31c: eeb48be0 vcmpe.f64 d8, d16 + 320: eef1fa10 vmrs APSR_nzcv, fpscr + 324: b3a02000 movlt r2, #0 + 328: baffffb2 blt 1f8 <__rem_pio2_large+0x1f8> + 32c: e35b0000 cmp fp, #0 + 330: ee193a10 vmov r3, s18 + 334: d3a02002 movle r2, #2 + 338: def70b00 vmovle.f64 d16, #112 ; 0x3f800000 1.0 + 33c: e2833001 add r3, r3, #1 + 340: ee093a10 vmov s18, r3 + 344: de308bc8 vsuble.f64 d8, d16, d8 + 348: daffffaa ble 1f8 <__rem_pio2_large+0x1f8> + 34c: e3a02002 mov r2, #2 + 350: ea000009 b 37c <__rem_pio2_large+0x37c> + 354: e08d310b add r3, sp, fp, lsl #2 + 358: e5932014 ldr r2, [r3, #20] + 35c: e1a02bc2 asr r2, r2, #23 + 360: e3520000 cmp r2, #0 + 364: daffffa3 ble 1f8 <__rem_pio2_large+0x1f8> + 368: ee193a10 vmov r3, s18 + 36c: e35b0000 cmp fp, #0 + 370: e2833001 add r3, r3, #1 + 374: ee093a10 vmov s18, r3 + 378: da00009b ble 5ec <__rem_pio2_large+0x5ec> + 37c: e1a03007 mov r3, r7 + 380: e3a00000 mov r0, #0 + 384: e4931004 ldr r1, [r3], #4 + 388: e3510000 cmp r1, #0 + 38c: 0a000089 beq 5b8 <__rem_pio2_large+0x5b8> + 390: e2611401 rsb r1, r1, #16777216 ; 0x1000000 + 394: e3e0c4ff mvn ip, #-16777216 ; 0xff000000 + 398: e5031004 str r1, [r3, #-4] + 39c: ea000002 b 3ac <__rem_pio2_large+0x3ac> + 3a0: e5931000 ldr r1, [r3] + 3a4: e04c1001 sub r1, ip, r1 + 3a8: e4831004 str r1, [r3], #4 + 3ac: e2800001 add r0, r0, #1 + 3b0: e15b0000 cmp fp, r0 + 3b4: cafffff9 bgt 3a0 <__rem_pio2_large+0x3a0> + 3b8: e3a01001 mov r1, #1 + 3bc: e35a0000 cmp sl, #0 + 3c0: da000009 ble 3ec <__rem_pio2_large+0x3ec> + 3c4: e35a0001 cmp sl, #1 + 3c8: 0a00009e beq 648 <__rem_pio2_large+0x648> + 3cc: e35a0002 cmp sl, #2 + 3d0: 1a000005 bne 3ec <__rem_pio2_large+0x3ec> + 3d4: e24b3001 sub r3, fp, #1 + 3d8: e28d0f92 add r0, sp, #584 ; 0x248 + 3dc: e0803103 add r3, r0, r3, lsl #2 + 3e0: e5130230 ldr r0, [r3, #-560] ; 0xfffffdd0 + 3e4: e7f50050 ubfx r0, r0, #0, #22 + 3e8: e5030230 str r0, [r3, #-560] ; 0xfffffdd0 + 3ec: e3520002 cmp r2, #2 + 3f0: 1affff80 bne 1f8 <__rem_pio2_large+0x1f8> + 3f4: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + 3f8: e3510000 cmp r1, #0 + 3fc: ee308b48 vsub.f64 d8, d0, d8 + 400: 0affff7c beq 1f8 <__rem_pio2_large+0x1f8> + 404: e1a0000a mov r0, sl + 408: e58d2014 str r2, [sp, #20] + 40c: ebfffffe bl 0 <__rem_pio2_large> + 40c: R_ARM_CALL scalbn + 410: ee388b40 vsub.f64 d8, d8, d0 + 414: e59d2014 ldr r2, [sp, #20] + 418: eeb58b40 vcmp.f64 d8, #0.0 + 41c: eef1fa10 vmrs APSR_nzcv, fpscr + 420: 0affff77 beq 204 <__rem_pio2_large+0x204> + 424: e59d3010 ldr r3, [sp, #16] + 428: eeb00b48 vmov.f64 d0, d8 + 42c: e26a0000 rsb r0, sl, #0 + 430: e59d5000 ldr r5, [sp] + 434: e58d2004 str r2, [sp, #4] + 438: e58d3000 str r3, [sp] + 43c: ebfffffe bl 0 <__rem_pio2_large> + 43c: R_ARM_CALL scalbn + 440: eddf2b36 vldr d18, [pc, #216] ; 520 <__rem_pio2_large+0x520> + 444: eef00b40 vmov.f64 d16, d0 + 448: e59d3000 ldr r3, [sp] + 44c: e59d2004 ldr r2, [sp, #4] + 450: eeb40be2 vcmpe.f64 d0, d18 + 454: eef1fa10 vmrs APSR_nzcv, fpscr + 458: ba0000d2 blt 7a8 <__rem_pio2_large+0x7a8> + 45c: eddf1b2d vldr d17, [pc, #180] ; 518 <__rem_pio2_large+0x518> + 460: e28b4001 add r4, fp, #1 + 464: e28aa018 add sl, sl, #24 + 468: e08db10b add fp, sp, fp, lsl #2 + 46c: e08d1104 add r1, sp, r4, lsl #2 + 470: ee601b21 vmul.f64 d17, d0, d17 + 474: eebd7be1 vcvt.s32.f64 s14, d17 + 478: eef81bc7 vcvt.f64.s32 d17, s14 + 47c: ee410be2 vmls.f64 d16, d17, d18 + 480: eefd7be0 vcvt.s32.f64 s15, d16 + 484: edcb7a06 vstr s15, [fp, #24] + 488: ed817a06 vstr s14, [r1, #24] + 48c: e1a0000a mov r0, sl + 490: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + 494: e1cd20f0 strd r2, [sp] + 498: ebfffffe bl 0 <__rem_pio2_large> + 498: R_ARM_CALL scalbn + 49c: e1cd20d0 ldrd r2, [sp] + 4a0: e3540000 cmp r4, #0 + 4a4: ba0000ca blt 7d4 <__rem_pio2_large+0x7d4> + 4a8: e284c001 add ip, r4, #1 + 4ac: e28def6a add lr, sp, #424 ; 0x1a8 + 4b0: e0877104 add r7, r7, r4, lsl #2 + 4b4: eddf2b17 vldr d18, [pc, #92] ; 518 <__rem_pio2_large+0x518> + 4b8: e1a0c18c lsl ip, ip, #3 + 4bc: e08e100c add r1, lr, ip + 4c0: e4170004 ldr r0, [r7], #-4 + 4c4: ee070a90 vmov s15, r0 + 4c8: eef80be7 vcvt.f64.s32 d16, s15 + 4cc: ee600b80 vmul.f64 d16, d16, d0 + 4d0: ee200b22 vmul.f64 d0, d0, d18 + 4d4: ed610b02 vstmdb r1!, {d16} + 4d8: e151000e cmp r1, lr + 4dc: 1afffff7 bne 4c0 <__rem_pio2_large+0x4c0> + 4e0: e28d8f42 add r8, sp, #264 ; 0x108 + 4e4: e24c0008 sub r0, ip, #8 + 4e8: e0816000 add r6, r1, r0 + 4ec: e1a09008 mov r9, r8 + 4f0: e1a07004 mov r7, r4 + 4f4: e3a0e000 mov lr, #0 + 4f8: e3550000 cmp r5, #0 + 4fc: ba000075 blt 6d8 <__rem_pio2_large+0x6d8> + 500: e3000000 movw r0, #0 + 500: R_ARM_MOVW_ABS_NC PIo2 + 504: e3400000 movt r0, #0 + 504: R_ARM_MOVT_ABS PIo2 + 508: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 50c: e1a0a006 mov sl, r6 + 510: e3a01000 mov r1, #0 + 514: ea00000a b 544 <__rem_pio2_large+0x544> + 518: 00000000 .word 0x00000000 + 51c: 3e700000 .word 0x3e700000 + 520: 00000000 .word 0x00000000 + 524: 41700000 .word 0x41700000 + ... + 530: ecf02b02 vldmia r0!, {d18} + 534: e1550001 cmp r5, r1 + 538: ecfa1b02 vldmia sl!, {d17} + 53c: ee420ba1 vmla.f64 d16, d18, d17 + 540: ba000002 blt 550 <__rem_pio2_large+0x550> + 544: e151000e cmp r1, lr + 548: e2811001 add r1, r1, #1 + 54c: dafffff7 ble 530 <__rem_pio2_large+0x530> + 550: e2477001 sub r7, r7, #1 + 554: e28ee001 add lr, lr, #1 + 558: e2466008 sub r6, r6, #8 + 55c: e3770001 cmn r7, #1 + 560: ece90b02 vstmia r9!, {d16} + 564: 1affffe3 bne 4f8 <__rem_pio2_large+0x4f8> + 568: e59d1280 ldr r1, [sp, #640] ; 0x280 + 56c: e3510002 cmp r1, #2 + 570: ca00005a bgt 6e0 <__rem_pio2_large+0x6e0> + 574: e3510000 cmp r1, #0 + 578: ca00003d bgt 674 <__rem_pio2_large+0x674> + 57c: 0d5f0b17 vldreq d16, [pc, #-92] ; 528 <__rem_pio2_large+0x528> + 580: 0088c00c addeq ip, r8, ip + 584: 1a000006 bne 5a4 <__rem_pio2_large+0x5a4> + 588: ed7c1b02 vldmdb ip!, {d17} + 58c: ee700ba1 vadd.f64 d16, d16, d17 + 590: e15c0008 cmp ip, r8 + 594: 1afffffb bne 588 <__rem_pio2_large+0x588> + 598: e3520000 cmp r2, #0 + 59c: 1ef10b60 vnegne.f64 d16, d16 + 5a0: edc30b00 vstr d16, [r3] + 5a4: ee193a10 vmov r3, s18 + 5a8: e2030007 and r0, r3, #7 + 5ac: e28ddf93 add sp, sp, #588 ; 0x24c + 5b0: ecbd8b04 vpop {d8-d9} + 5b4: e8bd8ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 5b8: e2800001 add r0, r0, #1 + 5bc: e15b0000 cmp fp, r0 + 5c0: caffff6f bgt 384 <__rem_pio2_large+0x384> + 5c4: eaffff7c b 3bc <__rem_pio2_large+0x3bc> + 5c8: e2800001 add r0, r0, #1 + 5cc: e35b0000 cmp fp, #0 + 5d0: ee090a10 vmov s18, r0 + 5d4: caffff68 bgt 37c <__rem_pio2_large+0x37c> + 5d8: e35a0001 cmp sl, #1 + 5dc: 0a000084 beq 7f4 <__rem_pio2_large+0x7f4> + 5e0: e35a0002 cmp sl, #2 + 5e4: 07f53053 ubfxeq r3, r3, #0, #22 + 5e8: 05013230 streq r3, [r1, #-560] ; 0xfffffdd0 + 5ec: e3520002 cmp r2, #2 + 5f0: 1affff00 bne 1f8 <__rem_pio2_large+0x1f8> + 5f4: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + 5f8: ee308bc8 vsub.f64 d8, d16, d8 + 5fc: eafffefd b 1f8 <__rem_pio2_large+0x1f8> + 600: e1a01002 mov r1, r2 + 604: eaffff15 b 260 <__rem_pio2_large+0x260> + 608: e24b4001 sub r4, fp, #1 + 60c: e59d5000 ldr r5, [sp] + 610: e59d3010 ldr r3, [sp, #16] + 614: e24aa018 sub sl, sl, #24 + 618: e08d1104 add r1, sp, r4, lsl #2 + 61c: e5911018 ldr r1, [r1, #24] + 620: e3510000 cmp r1, #0 + 624: 1affff98 bne 48c <__rem_pio2_large+0x48c> + 628: e24b1107 sub r1, fp, #-1073741823 ; 0xc0000001 + 62c: e0871101 add r1, r7, r1, lsl #2 + 630: e5310004 ldr r0, [r1, #-4]! + 634: e2444001 sub r4, r4, #1 + 638: e24aa018 sub sl, sl, #24 + 63c: e3500000 cmp r0, #0 + 640: 0afffffa beq 630 <__rem_pio2_large+0x630> + 644: eaffff90 b 48c <__rem_pio2_large+0x48c> + 648: e24b3001 sub r3, fp, #1 + 64c: e28d0f92 add r0, sp, #584 ; 0x248 + 650: e0803103 add r3, r0, r3, lsl #2 + 654: e5130230 ldr r0, [r3, #-560] ; 0xfffffdd0 + 658: e7f60050 ubfx r0, r0, #0, #23 + 65c: e5030230 str r0, [r3, #-560] ; 0xfffffdd0 + 660: eaffff61 b 3ec <__rem_pio2_large+0x3ec> + 664: e3a02000 mov r2, #0 + 668: e58d2004 str r2, [sp, #4] + 66c: e3e02017 mvn r2, #23 + 670: eafffe7b b 64 <__rem_pio2_large+0x64> + 674: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 678: eddd0b42 vldr d16, [sp, #264] ; 0x108 + 67c: e088c00c add ip, r8, ip + 680: ed7c2b02 vldmdb ip!, {d18} + 684: ee711ba2 vadd.f64 d17, d17, d18 + 688: e15c0008 cmp ip, r8 + 68c: 1afffffb bne 680 <__rem_pio2_large+0x680> + 690: e3520000 cmp r2, #0 + 694: 1a000048 bne 7bc <__rem_pio2_large+0x7bc> + 698: ee700be1 vsub.f64 d16, d16, d17 + 69c: e3540000 cmp r4, #0 + 6a0: edc31b00 vstr d17, [r3] + 6a4: 0a000009 beq 6d0 <__rem_pio2_large+0x6d0> + 6a8: e28d0e11 add r0, sp, #272 ; 0x110 + 6ac: e3a01001 mov r1, #1 + 6b0: ecf01b02 vldmia r0!, {d17} + 6b4: e2811001 add r1, r1, #1 + 6b8: e1540001 cmp r4, r1 + 6bc: ee700ba1 vadd.f64 d16, d16, d17 + 6c0: aafffffa bge 6b0 <__rem_pio2_large+0x6b0> + 6c4: e3520000 cmp r2, #0 + 6c8: 0a000000 beq 6d0 <__rem_pio2_large+0x6d0> + 6cc: eef10b60 vneg.f64 d16, d16 + 6d0: edc30b02 vstr d16, [r3, #8] + 6d4: eaffffb2 b 5a4 <__rem_pio2_large+0x5a4> + 6d8: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 6dc: eaffff9b b 550 <__rem_pio2_large+0x550> + 6e0: e59d1280 ldr r1, [sp, #640] ; 0x280 + 6e4: e3510003 cmp r1, #3 + 6e8: 1affffad bne 5a4 <__rem_pio2_large+0x5a4> + 6ec: e3540000 cmp r4, #0 + 6f0: 0a000047 beq 814 <__rem_pio2_large+0x814> + 6f4: e1a0c184 lsl ip, r4, #3 + 6f8: e088e00c add lr, r8, ip + 6fc: e1a0100e mov r1, lr + 700: e1a0000e mov r0, lr + 704: edde1b00 vldr d17, [lr] + 708: ed700b02 vldmdb r0!, {d16} + 70c: eef02b61 vmov.f64 d18, d17 + 710: ee711ba0 vadd.f64 d17, d17, d16 + 714: e1500008 cmp r0, r8 + 718: ee700be1 vsub.f64 d16, d16, d17 + 71c: edc01b00 vstr d17, [r0] + 720: ee700ba2 vadd.f64 d16, d16, d18 + 724: edc00b02 vstr d16, [r0, #8] + 728: 1afffff6 bne 708 <__rem_pio2_large+0x708> + 72c: e3540001 cmp r4, #1 + 730: 0a000037 beq 814 <__rem_pio2_large+0x814> + 734: edde1b00 vldr d17, [lr] + 738: e2880008 add r0, r8, #8 + 73c: ed710b02 vldmdb r1!, {d16} + 740: eef02b61 vmov.f64 d18, d17 + 744: ee711ba0 vadd.f64 d17, d17, d16 + 748: e1500001 cmp r0, r1 + 74c: ee700be1 vsub.f64 d16, d16, d17 + 750: edc11b00 vstr d17, [r1] + 754: ee700ba2 vadd.f64 d16, d16, d18 + 758: edc10b02 vstr d16, [r1, #8] + 75c: 1afffff6 bne 73c <__rem_pio2_large+0x73c> + 760: e28c1008 add r1, ip, #8 + 764: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 768: e0881001 add r1, r8, r1 + 76c: e2888010 add r8, r8, #16 + 770: ed711b02 vldmdb r1!, {d17} + 774: ee700ba1 vadd.f64 d16, d16, d17 + 778: e1580001 cmp r8, r1 + 77c: 1afffffb bne 770 <__rem_pio2_large+0x770> + 780: e3520000 cmp r2, #0 + 784: eddd2b42 vldr d18, [sp, #264] ; 0x108 + 788: eddd1b44 vldr d17, [sp, #272] ; 0x110 + 78c: 1ef12b62 vnegne.f64 d18, d18 + 790: 1ef10b60 vnegne.f64 d16, d16 + 794: 1ef11b61 vnegne.f64 d17, d17 + 798: edc32b00 vstr d18, [r3] + 79c: edc31b02 vstr d17, [r3, #8] + 7a0: edc30b04 vstr d16, [r3, #16] + 7a4: eaffff7e b 5a4 <__rem_pio2_large+0x5a4> + 7a8: eefd7bc0 vcvt.s32.f64 s15, d0 + 7ac: e08d110b add r1, sp, fp, lsl #2 + 7b0: e1a0400b mov r4, fp + 7b4: edc17a06 vstr s15, [r1, #24] + 7b8: eaffff33 b 48c <__rem_pio2_large+0x48c> + 7bc: eef12b61 vneg.f64 d18, d17 + 7c0: ee700be1 vsub.f64 d16, d16, d17 + 7c4: e3540000 cmp r4, #0 + 7c8: edc32b00 vstr d18, [r3] + 7cc: 1affffb5 bne 6a8 <__rem_pio2_large+0x6a8> + 7d0: eaffffbd b 6cc <__rem_pio2_large+0x6cc> + 7d4: e59d1280 ldr r1, [sp, #640] ; 0x280 + 7d8: e3510002 cmp r1, #2 + 7dc: ca000009 bgt 808 <__rem_pio2_large+0x808> + 7e0: e3510000 cmp r1, #0 + 7e4: ca00000c bgt 81c <__rem_pio2_large+0x81c> + 7e8: 0d5f0bb2 vldreq d16, [pc, #-712] ; 528 <__rem_pio2_large+0x528> + 7ec: 0affff69 beq 598 <__rem_pio2_large+0x598> + 7f0: eaffff6b b 5a4 <__rem_pio2_large+0x5a4> + 7f4: e7f63053 ubfx r3, r3, #0, #23 + 7f8: e3520002 cmp r2, #2 + 7fc: e5013230 str r3, [r1, #-560] ; 0xfffffdd0 + 800: 1afffe7c bne 1f8 <__rem_pio2_large+0x1f8> + 804: eaffff7a b 5f4 <__rem_pio2_large+0x5f4> + 808: e59d1280 ldr r1, [sp, #640] ; 0x280 + 80c: e3510003 cmp r1, #3 + 810: 1affff63 bne 5a4 <__rem_pio2_large+0x5a4> + 814: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 818: eaffffd8 b 780 <__rem_pio2_large+0x780> + 81c: eddd0b42 vldr d16, [sp, #264] ; 0x108 + 820: e3520000 cmp r2, #0 + 824: 0a000005 beq 840 <__rem_pio2_large+0x840> + 828: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 82c: e3a00000 mov r0, #0 + 830: e3a01102 mov r1, #-2147483648 ; 0x80000000 + 834: e1c300f0 strd r0, [r3] + 838: ee700be1 vsub.f64 d16, d16, d17 + 83c: eaffffa2 b 6cc <__rem_pio2_large+0x6cc> + 840: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 844: ee700be1 vsub.f64 d16, d16, d17 + 848: edc31b00 vstr d17, [r3] + 84c: eaffff9f b 6d0 <__rem_pio2_large+0x6d0> + +Disassembly of section .text.__rem_pio2f: + +00000000 <__rem_pio2f>: + 0: e92d4030 push {r4, r5, lr} + 4: ee105a10 vmov r5, s0 + 8: e3002fda movw r2, #4058 ; 0xfda + c: e3442dc9 movt r2, #19913 ; 0x4dc9 + 10: e24dd01c sub sp, sp, #28 + 14: e1a04000 mov r4, r0 + 18: e3c53102 bic r3, r5, #-2147483648 ; 0x80000000 + 1c: e1530002 cmp r3, r2 + 20: 9a00001c bls 98 <__rem_pio2f+0x98> + 24: e30f2fff movw r2, #65535 ; 0xffff + 28: e3472f7f movt r2, #32639 ; 0x7f7f + 2c: e1530002 cmp r3, r2 + 30: 9a000005 bls 4c <__rem_pio2f+0x4c> + 34: ee300a40 vsub.f32 s0, s0, s0 + 38: e3a00000 mov r0, #0 + 3c: eef70ac0 vcvt.f64.f32 d16, s0 + 40: edc40b00 vstr d16, [r4] + 44: e28dd01c add sp, sp, #28 + 48: e8bd8030 pop {r4, r5, pc} + 4c: e1a02ba3 lsr r2, r3, #23 + 50: e3a01000 mov r1, #0 + 54: e2422096 sub r2, r2, #150 ; 0x96 + 58: e58d1000 str r1, [sp] + 5c: e28d0008 add r0, sp, #8 + 60: e28d1010 add r1, sp, #16 + 64: e0433b82 sub r3, r3, r2, lsl #23 + 68: ee073a90 vmov s15, r3 + 6c: e3a03001 mov r3, #1 + 70: eef70ae7 vcvt.f64.f32 d16, s15 + 74: edcd0b02 vstr d16, [sp, #8] + 78: ebfffffe bl 0 <__rem_pio2f> + 78: R_ARM_CALL __rem_pio2_large + 7c: eddd0b04 vldr d16, [sp, #16] + 80: e3550000 cmp r5, #0 + 84: b2600000 rsblt r0, r0, #0 + 88: bef10b60 vneglt.f64 d16, d16 + 8c: edc40b00 vstr d16, [r4] + 90: e28dd01c add sp, sp, #28 + 94: e8bd8030 pop {r4, r5, pc} + 98: eddf0b22 vldr d16, [pc, #136] ; 128 <__rem_pio2f+0x128> + 9c: eef72ac0 vcvt.f64.f32 d18, s0 + a0: eddf6b22 vldr d22, [pc, #136] ; 130 <__rem_pio2f+0x130> + a4: eddf4b23 vldr d20, [pc, #140] ; 138 <__rem_pio2f+0x138> + a8: eef01b60 vmov.f64 d17, d16 + ac: eddf3b23 vldr d19, [pc, #140] ; 140 <__rem_pio2f+0x140> + b0: ee421ba6 vmla.f64 d17, d18, d22 + b4: eddf5b23 vldr d21, [pc, #140] ; 148 <__rem_pio2f+0x148> + b8: ee711be0 vsub.f64 d17, d17, d16 + bc: eef00b62 vmov.f64 d16, d18 + c0: ee410be4 vmls.f64 d16, d17, d20 + c4: eefd7be1 vcvt.s32.f64 s15, d17 + c8: ee410be3 vmls.f64 d16, d17, d19 + cc: ee170a90 vmov r0, s15 + d0: eef40be5 vcmpe.f64 d16, d21 + d4: eef1fa10 vmrs APSR_nzcv, fpscr + d8: 4a00000a bmi 108 <__rem_pio2f+0x108> + dc: eddf5b1b vldr d21, [pc, #108] ; 150 <__rem_pio2f+0x150> + e0: eef40be5 vcmpe.f64 d16, d21 + e4: eef1fa10 vmrs APSR_nzcv, fpscr + e8: daffffd4 ble 40 <__rem_pio2f+0x40> + ec: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + f0: e2800001 add r0, r0, #1 + f4: ee711ba0 vadd.f64 d17, d17, d16 + f8: ee412be4 vmls.f64 d18, d17, d20 + fc: eef00b62 vmov.f64 d16, d18 + 100: ee410be3 vmls.f64 d16, d17, d19 + 104: eaffffcd b 40 <__rem_pio2f+0x40> + 108: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + 10c: e2400001 sub r0, r0, #1 + 110: ee711be0 vsub.f64 d17, d17, d16 + 114: ee412be4 vmls.f64 d18, d17, d20 + 118: eef00b62 vmov.f64 d16, d18 + 11c: ee410be3 vmls.f64 d16, d17, d19 + 120: eaffffc6 b 40 <__rem_pio2f+0x40> + 124: e320f000 nop {0} + 128: 00000000 .word 0x00000000 + 12c: 43380000 .word 0x43380000 + 130: 6dc9c883 .word 0x6dc9c883 + 134: 3fe45f30 .word 0x3fe45f30 + 138: 50000000 .word 0x50000000 + 13c: 3ff921fb .word 0x3ff921fb + 140: 611a6263 .word 0x611a6263 + 144: 3e5110b4 .word 0x3e5110b4 + 148: 60000000 .word 0x60000000 + 14c: bfe921fb .word 0xbfe921fb + 150: 60000000 .word 0x60000000 + 154: 3fe921fb .word 0x3fe921fb + +Disassembly of section .text.__sindf: + +00000000 <__sindf>: + 0: ee600b00 vmul.f64 d16, d0, d0 + 4: eddf3b0b vldr d19, [pc, #44] ; 38 <__sindf+0x38> + 8: eddf2b0c vldr d18, [pc, #48] ; 40 <__sindf+0x40> + c: eddf4b0d vldr d20, [pc, #52] ; 48 <__sindf+0x48> + 10: eddf1b0e vldr d17, [pc, #56] ; 50 <__sindf+0x50> + 14: ee502ba3 vnmls.f64 d18, d16, d19 + 18: ee603b20 vmul.f64 d19, d0, d16 + 1c: ee501ba4 vnmls.f64 d17, d16, d20 + 20: ee600ba0 vmul.f64 d16, d16, d16 + 24: ee600ba3 vmul.f64 d16, d16, d19 + 28: ee020ba3 vmla.f64 d0, d18, d19 + 2c: ee000ba1 vmla.f64 d0, d16, d17 + 30: eeb70bc0 vcvt.f32.f64 s0, d0 + 34: e12fff1e bx lr + 38: 896efbb2 .word 0x896efbb2 + 3c: 3f811110 .word 0x3f811110 + 40: 54cbac77 .word 0x54cbac77 + 44: 3fc55555 .word 0x3fc55555 + 48: 8c3b46a7 .word 0x8c3b46a7 + 4c: 3ec6cd87 .word 0x3ec6cd87 + 50: e2cae774 .word 0xe2cae774 + 54: 3f2a00f9 .word 0x3f2a00f9 + +Disassembly of section .text.__init_ssp: + +00000000 <__init_ssp>: + 0: e2501000 subs r1, r0, #0 + 4: 0a000009 beq 30 <__init_ssp+0x30> + 8: e92d4010 push {r4, lr} + c: e3004000 movw r4, #0 + c: R_ARM_MOVW_ABS_NC __stack_chk_guard + 10: e3404000 movt r4, #0 + 10: R_ARM_MOVT_ABS __stack_chk_guard + 14: e3a02004 mov r2, #4 + 18: e1a00004 mov r0, r4 + 1c: ebfffffe bl 0 + 1c: R_ARM_CALL memcpy + 20: e5943000 ldr r3, [r4] + 24: ee1d2f70 mrc 15, 0, r2, cr13, cr0, {3} + 28: e5023008 str r3, [r2, #-8] + 2c: e8bd8010 pop {r4, pc} + 30: e3002000 movw r2, #0 + 30: R_ARM_MOVW_ABS_NC __stack_chk_guard + 34: e3402000 movt r2, #0 + 34: R_ARM_MOVT_ABS __stack_chk_guard + 38: e3043e6d movw r3, #20077 ; 0x4e6d + 3c: e34431c6 movt r3, #16838 ; 0x41c6 + 40: e0030293 mul r3, r3, r2 + 44: e5823000 str r3, [r2] + 48: ee1d2f70 mrc 15, 0, r2, cr13, cr0, {3} + 4c: e5023008 str r3, [r2, #-8] + 50: e12fff1e bx lr + +Disassembly of section .text.__stack_chk_fail: + +00000000 <__stack_chk_fail>: + 0: e7f000f0 .word 0xe7f000f0 + 4: e12fff1e bx lr + +Disassembly of section .text.__tandf: + +00000000 <__tandf>: + 0: ee600b00 vmul.f64 d16, d0, d0 + 4: eddf4b13 vldr d20, [pc, #76] ; 58 <__tandf+0x58> + 8: eddf3b14 vldr d19, [pc, #80] ; 60 <__tandf+0x60> + c: e3500000 cmp r0, #0 + 10: eddf6b14 vldr d22, [pc, #80] ; 68 <__tandf+0x68> + 14: eddf5b15 vldr d21, [pc, #84] ; 70 <__tandf+0x70> + 18: ee403ba4 vmla.f64 d19, d16, d20 + 1c: eddf1b15 vldr d17, [pc, #84] ; 78 <__tandf+0x78> + 20: eddf2b16 vldr d18, [pc, #88] ; 80 <__tandf+0x80> + 24: ee604ba0 vmul.f64 d20, d16, d16 + 28: ee402ba5 vmla.f64 d18, d16, d21 + 2c: ee401ba6 vmla.f64 d17, d16, d22 + 30: ee600b20 vmul.f64 d16, d0, d16 + 34: ee645ba0 vmul.f64 d21, d20, d16 + 38: ee431ba4 vmla.f64 d17, d19, d20 + 3c: ee020ba0 vmla.f64 d0, d18, d16 + 40: 1eff0b00 vmovne.f64 d16, #240 ; 0xbf800000 -1.0 + 44: ee010ba5 vmla.f64 d0, d17, d21 + 48: 1e800b80 vdivne.f64 d0, d16, d0 + 4c: eeb70bc0 vcvt.f32.f64 s0, d0 + 50: e12fff1e bx lr + 54: e320f000 nop {0} + 58: bf971bcd .word 0xbf971bcd + 5c: 3f8362b9 .word 0x3f8362b9 + 60: fcecf44e .word 0xfcecf44e + 64: 3f685dad .word 0x3f685dad + 68: 908c33ce .word 0x908c33ce + 6c: 3f991df3 .word 0x3f991df3 + 70: 38999f72 .word 0x38999f72 + 74: 3fc112fd .word 0x3fc112fd + 78: 1d865afe .word 0x1d865afe + 7c: 3fab54c9 .word 0x3fab54c9 + 80: 3418c99f .word 0x3418c99f + 84: 3fd5554d .word 0x3fd5554d + +Disassembly of section .text.acosf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 8: e35305fe cmp r3, #1065353216 ; 0x3f800000 + c: 3a000004 bcc 24 + 10: 1a00002c bne c8 + 14: e3520000 cmp r2, #0 + 18: ba000040 blt 120 + 1c: ed9f0a57 vldr s0, [pc, #348] ; 180 + 20: e12fff1e bx lr + 24: e353043f cmp r3, #1056964608 ; 0x3f000000 + 28: 2a000005 bcs 44 + 2c: e35305ca cmp r3, #847249408 ; 0x32800000 + 30: 8a000028 bhi d8 + 34: eddf7a52 vldr s15, [pc, #328] ; 184 + 38: ed9f0a52 vldr s0, [pc, #328] ; 188 + 3c: ee300a27 vadd.f32 s0, s0, s15 + 40: e12fff1e bx lr + 44: e92d4010 push {r4, lr} + 48: e3520000 cmp r2, #0 + 4c: eef67a00 vmov.f32 s15, #96 ; 0x3f000000 0.5 + 50: ed2d8b02 vpush {d8} + 54: eef78a00 vmov.f32 s17, #112 ; 0x3f800000 1.0 + 58: ba000034 blt 130 + 5c: ee380ac0 vsub.f32 s0, s17, s0 + 60: ee208a27 vmul.f32 s16, s0, s15 + 64: eeb00a48 vmov.f32 s0, s16 + 68: ebfffffe bl 0 + 68: R_ARM_CALL sqrtf + 6c: ed9f7a46 vldr s14, [pc, #280] ; 18c + 70: ed9f6a46 vldr s12, [pc, #280] ; 190 + 74: ee103a10 vmov r3, s0 + 78: eddf6a45 vldr s13, [pc, #276] ; 194 + 7c: eeb05a48 vmov.f32 s10, s16 + 80: eddf7a44 vldr s15, [pc, #272] ; 198 + 84: ee186a07 vnmls.f32 s12, s16, s14 + 88: eeb07a40 vmov.f32 s14, s0 + 8c: ee488a26 vmla.f32 s17, s16, s13 + 90: e7cb301f bfc r3, #0, #12 + 94: ee063a90 vmov s13, r3 + 98: ee065ae6 vmls.f32 s10, s13, s13 + 9c: ee705a26 vadd.f32 s11, s0, s13 + a0: ee467a08 vmla.f32 s15, s12, s16 + a4: ee850a25 vdiv.f32 s0, s10, s11 + a8: ee677a88 vmul.f32 s15, s15, s16 + ac: ee876aa8 vdiv.f32 s12, s15, s17 + b0: eef07a40 vmov.f32 s15, s0 + b4: ee467a07 vmla.f32 s15, s12, s14 + b8: ee370aa6 vadd.f32 s0, s15, s13 + bc: ee300a00 vadd.f32 s0, s0, s0 + c0: ecbd8b02 vpop {d8} + c4: e8bd8010 pop {r4, pc} + c8: ee707a40 vsub.f32 s15, s0, s0 + cc: ed9f7a2b vldr s14, [pc, #172] ; 180 + d0: ee870a27 vdiv.f32 s0, s14, s15 + d4: e12fff1e bx lr + d8: ee606a00 vmul.f32 s13, s0, s0 + dc: ed9f4a2a vldr s8, [pc, #168] ; 18c + e0: ed9f5a2a vldr s10, [pc, #168] ; 190 + e4: eef75a00 vmov.f32 s11, #112 ; 0x3f800000 1.0 + e8: ed9f7a2a vldr s14, [pc, #168] ; 198 + ec: eddf4a28 vldr s9, [pc, #160] ; 194 + f0: ee165a84 vnmls.f32 s10, s13, s8 + f4: ed9f6a28 vldr s12, [pc, #160] ; 19c + f8: eddf7a22 vldr s15, [pc, #136] ; 188 + fc: ee465aa4 vmla.f32 s11, s13, s9 + 100: ee057a26 vmla.f32 s14, s10, s13 + 104: ee277a26 vmul.f32 s14, s14, s13 + 108: eec76a25 vdiv.f32 s13, s14, s11 + 10c: eeb07a46 vmov.f32 s14, s12 + 110: ee067ac0 vmls.f32 s14, s13, s0 + 114: ee300a47 vsub.f32 s0, s0, s14 + 118: ee370ac0 vsub.f32 s0, s15, s0 + 11c: e12fff1e bx lr + 120: eddf7a17 vldr s15, [pc, #92] ; 184 + 124: ed9f0a1d vldr s0, [pc, #116] ; 1a0 + 128: ee300a27 vadd.f32 s0, s0, s15 + 12c: e12fff1e bx lr + 130: ee300a28 vadd.f32 s0, s0, s17 + 134: ee208a27 vmul.f32 s16, s0, s15 + 138: eeb00a48 vmov.f32 s0, s16 + 13c: ebfffffe bl 0 + 13c: R_ARM_CALL sqrtf + 140: ed9f5a11 vldr s10, [pc, #68] ; 18c + 144: ed9f6a11 vldr s12, [pc, #68] ; 190 + 148: eddf6a12 vldr s13, [pc, #72] ; 198 + 14c: eddf5a10 vldr s11, [pc, #64] ; 194 + 150: ee186a05 vnmls.f32 s12, s16, s10 + 154: ed9f7a10 vldr s14, [pc, #64] ; 19c + 158: eddf7a0a vldr s15, [pc, #40] ; 188 + 15c: ee488a25 vmla.f32 s17, s16, s11 + 160: ee466a08 vmla.f32 s13, s12, s16 + 164: ee666a88 vmul.f32 s13, s13, s16 + 168: ee866aa8 vdiv.f32 s12, s13, s17 + 16c: ee167a00 vnmls.f32 s14, s12, s0 + 170: ee377a00 vadd.f32 s14, s14, s0 + 174: ee370ac7 vsub.f32 s0, s15, s14 + 178: ee300a00 vadd.f32 s0, s0, s0 + 17c: eaffffcf b c0 + 180: 00000000 .word 0x00000000 + 184: 03800000 .word 0x03800000 + 188: 3fc90fda .word 0x3fc90fda + 18c: bc0dd36b .word 0xbc0dd36b + 190: 3d2f13ba .word 0x3d2f13ba + 194: bf34e5ae .word 0xbf34e5ae + 198: 3e2aaa75 .word 0x3e2aaa75 + 19c: 33a22168 .word 0x33a22168 + 1a0: 40490fda .word 0x40490fda + +Disassembly of section .text.asinf: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ee104a10 vmov r4, s0 + 8: eef07a40 vmov.f32 s15, s0 + c: ed2d8b02 vpush {d8} + 10: e3c43102 bic r3, r4, #-2147483648 ; 0x80000000 + 14: e35305fe cmp r3, #1065353216 ; 0x3f800000 + 18: 3a000009 bcc 44 + 1c: 1e777ae7 vsubne.f32 s15, s15, s15 + 20: 1d9f7a3a vldrne s14, [pc, #232] ; 110 + 24: 0eb70ac0 vcvteq.f64.f32 d0, s0 + 28: 0ddf0b34 vldreq d16, [pc, #208] ; 100 + 2c: 0ddf1b35 vldreq d17, [pc, #212] ; 108 + 30: 1e870a27 vdivne.f32 s0, s14, s15 + 34: 0e400b21 vmlaeq.f64 d16, d0, d17 + 38: 0eb70be0 vcvteq.f32.f64 s0, d16 + 3c: ecbd8b02 vpop {d8} + 40: e8bd8010 pop {r4, pc} + 44: e353043f cmp r3, #1056964608 ; 0x3f000000 + 48: 2a000011 bcs 94 + 4c: e2433502 sub r3, r3, #8388608 ; 0x800000 + 50: e3530439 cmp r3, #956301312 ; 0x39000000 + 54: 3afffff8 bcc 3c + 58: ee676aa7 vmul.f32 s13, s15, s15 + 5c: eddf4a2c vldr s9, [pc, #176] ; 114 + 60: eddf5a2c vldr s11, [pc, #176] ; 118 + 64: eeb76a00 vmov.f32 s12, #112 ; 0x3f800000 1.0 + 68: ed9f7a2b vldr s14, [pc, #172] ; 11c + 6c: ed9f5a2b vldr s10, [pc, #172] ; 120 + 70: ee565aa4 vnmls.f32 s11, s13, s9 + 74: ecbd8b02 vpop {d8} + 78: ee066a85 vmla.f32 s12, s13, s10 + 7c: ee057aa6 vmla.f32 s14, s11, s13 + 80: ee277a26 vmul.f32 s14, s14, s13 + 84: eec76a06 vdiv.f32 s13, s14, s12 + 88: ee467aa7 vmla.f32 s15, s13, s15 + 8c: eeb00a67 vmov.f32 s0, s15 + 90: e8bd8010 pop {r4, pc} + 94: eef78a00 vmov.f32 s17, #112 ; 0x3f800000 1.0 + 98: ebfffffe bl 0 + 98: R_ARM_CALL fabsf + 9c: eef67a00 vmov.f32 s15, #96 ; 0x3f000000 0.5 + a0: ee388ac0 vsub.f32 s16, s17, s0 + a4: ee288a27 vmul.f32 s16, s16, s15 + a8: eeb70ac8 vcvt.f64.f32 d0, s16 + ac: ebfffffe bl 0 + ac: R_ARM_CALL sqrt + b0: ed9f6a17 vldr s12, [pc, #92] ; 114 + b4: ed9f7a17 vldr s14, [pc, #92] ; 118 + b8: e3540000 cmp r4, #0 + bc: eddf7a16 vldr s15, [pc, #88] ; 11c + c0: eddf6a16 vldr s13, [pc, #88] ; 120 + c4: ee187a06 vnmls.f32 s14, s16, s12 + c8: eddf0b0e vldr d16, [pc, #56] ; 108 + cc: ee488a26 vmla.f32 s17, s16, s13 + d0: ee477a08 vmla.f32 s15, s14, s16 + d4: ee677a88 vmul.f32 s15, s15, s16 + d8: ee877aa8 vdiv.f32 s14, s15, s17 + dc: ecbd8b02 vpop {d8} + e0: eeb77ac7 vcvt.f64.f32 d7, s14 + e4: ee070b00 vmla.f64 d0, d7, d0 + e8: ee300b00 vadd.f64 d0, d0, d0 + ec: ee300bc0 vsub.f64 d0, d16, d0 + f0: eeb70bc0 vcvt.f32.f64 s0, d0 + f4: beb10a40 vneglt.f32 s0, s0 + f8: e8bd8010 pop {r4, pc} + fc: e320f000 nop {0} + 100: 00000000 .word 0x00000000 + 104: 38700000 .word 0x38700000 + 108: 54442d18 .word 0x54442d18 + 10c: 3ff921fb .word 0x3ff921fb + 110: 00000000 .word 0x00000000 + 114: bc0dd36b .word 0xbc0dd36b + 118: 3d2f13ba .word 0x3d2f13ba + 11c: 3e2aaa75 .word 0x3e2aaa75 + 120: bf34e5ae .word 0xbf34e5ae + +Disassembly of section .text.atan2f: + +00000000 : + 0: ee103a90 vmov r3, s1 + 4: e3a02000 mov r2, #0 + 8: e3472f80 movt r2, #32640 ; 0x7f80 + c: eef07a40 vmov.f32 s15, s0 + 10: e3c31102 bic r1, r3, #-2147483648 ; 0x80000000 + 14: e1510002 cmp r1, r2 + 18: 8a000024 bhi b0 + 1c: ee10ca10 vmov ip, s0 + 20: e3cc0102 bic r0, ip, #-2147483648 ; 0x80000000 + 24: e1500002 cmp r0, r2 + 28: 8a000020 bhi b0 + 2c: e35305fe cmp r3, #1065353216 ; 0x3f800000 + 30: 0a00002d beq ec + 34: e92d4010 push {r4, lr} + 38: e1a04f23 lsr r4, r3, #30 + 3c: e2044002 and r4, r4, #2 + 40: e3500000 cmp r0, #0 + 44: e1844fac orr r4, r4, ip, lsr #31 + 48: 0a00001a beq b8 + 4c: e3510000 cmp r1, #0 + 50: 0a00001e beq d0 + 54: e1510002 cmp r1, r2 + 58: 0a000024 beq f0 + 5c: e0402002 sub r2, r0, r2 + 60: e281340d add r3, r1, #218103808 ; 0xd000000 + 64: e16f2f12 clz r2, r2 + 68: e1a022a2 lsr r2, r2, #5 + 6c: e1500003 cmp r0, r3 + 70: 83822001 orrhi r2, r2, #1 + 74: e3520000 cmp r2, #0 + 78: 1a000014 bne d0 + 7c: e3140002 tst r4, #2 + 80: 0a000038 beq 168 + 84: e280040d add r0, r0, #218103808 ; 0xd000000 + 88: e1510000 cmp r1, r0 + 8c: 9a000021 bls 118 + 90: ed9f0a49 vldr s0, [pc, #292] ; 1bc + 94: e3540002 cmp r4, #2 + 98: 0a000023 beq 12c + 9c: ed9f7a47 vldr s14, [pc, #284] ; 1c0 + a0: eddf7a47 vldr s15, [pc, #284] ; 1c4 + a4: ee300a07 vadd.f32 s0, s0, s14 + a8: ee300a67 vsub.f32 s0, s0, s15 + ac: e8bd8010 pop {r4, pc} + b0: ee300aa7 vadd.f32 s0, s1, s15 + b4: e12fff1e bx lr + b8: e3540002 cmp r4, #2 + bc: 0a000008 beq e4 + c0: ed9f7a40 vldr s14, [pc, #256] ; 1c8 + c4: e3540003 cmp r4, #3 + c8: 0eb00a47 vmoveq.f32 s0, s14 + cc: e8bd8010 pop {r4, pc} + d0: eddf7a3d vldr s15, [pc, #244] ; 1cc + d4: e3140001 tst r4, #1 + d8: ed9f0a3c vldr s0, [pc, #240] ; 1d0 + dc: 0eb00a67 vmoveq.f32 s0, s15 + e0: e8bd8010 pop {r4, pc} + e4: ed9f0a36 vldr s0, [pc, #216] ; 1c4 + e8: e8bd8010 pop {r4, pc} + ec: eafffffe b 0 + ec: R_ARM_JUMP24 atanf + f0: e1500001 cmp r0, r1 + f4: 0a000011 beq 140 + f8: e2444001 sub r4, r4, #1 + fc: e3540002 cmp r4, #2 + 100: 8a00001f bhi 184 + 104: e3003000 movw r3, #0 + 104: R_ARM_MOVW_ABS_NC CSWTCH.7 + 108: e3403000 movt r3, #0 + 108: R_ARM_MOVT_ABS CSWTCH.7 + 10c: e0833104 add r3, r3, r4, lsl #2 + 110: ed930a00 vldr s0, [r3] + 114: e8bd8010 pop {r4, pc} + 118: ee870aa0 vdiv.f32 s0, s15, s1 + 11c: ebfffffe bl 0 + 11c: R_ARM_CALL fabsf + 120: ebfffffe bl 0 + 120: R_ARM_CALL atanf + 124: e3540002 cmp r4, #2 + 128: 1affffdb bne 9c + 12c: ed9f7a23 vldr s14, [pc, #140] ; 1c0 + 130: eddf7a23 vldr s15, [pc, #140] ; 1c4 + 134: ee300a07 vadd.f32 s0, s0, s14 + 138: ee370ac0 vsub.f32 s0, s15, s0 + 13c: e8bd8010 pop {r4, pc} + 140: e3540002 cmp r4, #2 + 144: 0a000016 beq 1a4 + 148: e3540003 cmp r4, #3 + 14c: 0a00000e beq 18c + 150: eddf7a1f vldr s15, [pc, #124] ; 1d4 + 154: e3540001 cmp r4, #1 + 158: ed9f7a1e vldr s14, [pc, #120] ; 1d8 + 15c: 1eb00a47 vmovne.f32 s0, s14 + 160: 0eb00a67 vmoveq.f32 s0, s15 + 164: e8bd8010 pop {r4, pc} + 168: ee870aa0 vdiv.f32 s0, s15, s1 + 16c: ebfffffe bl 0 + 16c: R_ARM_CALL fabsf + 170: ebfffffe bl 0 + 170: R_ARM_CALL atanf + 174: e3540001 cmp r4, #1 + 178: 18bd8010 popne {r4, pc} + 17c: eeb10a40 vneg.f32 s0, s0 + 180: e8bd8010 pop {r4, pc} + 184: ed9f0a0c vldr s0, [pc, #48] ; 1bc + 188: e8bd8010 pop {r4, pc} + 18c: eddf7a0c vldr s15, [pc, #48] ; 1c4 + 190: eef86a08 vmov.f32 s13, #136 ; 0xc0400000 -3.0 + 194: eeb57a00 vmov.f32 s14, #80 ; 0x3e800000 0.250 + 198: ee677aa6 vmul.f32 s15, s15, s13 + 19c: ee270a87 vmul.f32 s0, s15, s14 + 1a0: e8bd8010 pop {r4, pc} + 1a4: eddf7a06 vldr s15, [pc, #24] ; 1c4 + 1a8: eef06a08 vmov.f32 s13, #8 ; 0x40400000 3.0 + 1ac: eeb57a00 vmov.f32 s14, #80 ; 0x3e800000 0.250 + 1b0: ee677aa6 vmul.f32 s15, s15, s13 + 1b4: ee270a87 vmul.f32 s0, s15, s14 + 1b8: e8bd8010 pop {r4, pc} + 1bc: 00000000 .word 0x00000000 + 1c0: 33bbbd2e .word 0x33bbbd2e + 1c4: 40490fdb .word 0x40490fdb + 1c8: c0490fdb .word 0xc0490fdb + 1cc: 3fc90fdb .word 0x3fc90fdb + 1d0: bfc90fdb .word 0xbfc90fdb + 1d4: bf490fdb .word 0xbf490fdb + 1d8: 3f490fdb .word 0x3f490fdb + +Disassembly of section .text.atanf: + +00000000 : + 0: ee103a10 vmov r3, s0 + 4: e92d4030 push {r4, r5, lr} + 8: e30f2fff movw r2, #65535 ; 0xffff + c: e3442c7f movt r2, #19583 ; 0x4c7f + 10: eef07a40 vmov.f32 s15, s0 + 14: e24dd00c sub sp, sp, #12 + 18: e3c34102 bic r4, r3, #-2147483648 ; 0x80000000 + 1c: e1a05fa3 lsr r5, r3, #31 + 20: e1540002 cmp r4, r2 + 24: 9a000006 bls 44 + 28: e3a03000 mov r3, #0 + 2c: e3473f80 movt r3, #32640 ; 0x7f80 + 30: e1540003 cmp r4, r3 + 34: 9a000016 bls 94 + 38: eeb00a67 vmov.f32 s0, s15 + 3c: e28dd00c add sp, sp, #12 + 40: e8bd8030 pop {r4, r5, pc} + 44: e30f2fff movw r2, #65535 ; 0xffff + 48: e3432edf movt r2, #16095 ; 0x3edf + 4c: e1540002 cmp r4, r2 + 50: 8a000017 bhi b4 + 54: e35405e6 cmp r4, #964689920 ; 0x39800000 + 58: 3a000027 bcc fc + 5c: ee206a00 vmul.f32 s12, s0, s0 + 60: ed9f4a55 vldr s8, [pc, #340] ; 1bc + 64: ed9f5a55 vldr s10, [pc, #340] ; 1c0 + 68: eddf4a55 vldr s9, [pc, #340] ; 1c4 + 6c: ed9f7a55 vldr s14, [pc, #340] ; 1c8 + 70: ee666a06 vmul.f32 s13, s12, s12 + 74: eddf5a54 vldr s11, [pc, #336] ; 1cc + 78: ee065a84 vmla.f32 s10, s13, s8 + 7c: ee167aa4 vnmls.f32 s14, s13, s9 + 80: ee455a26 vmla.f32 s11, s10, s13 + 84: ee277a26 vmul.f32 s14, s14, s13 + 88: ee057a86 vmla.f32 s14, s11, s12 + 8c: ee477a40 vmls.f32 s15, s14, s0 + 90: eaffffe8 b 38 + 94: eddf7a4d vldr s15, [pc, #308] ; 1d0 + 98: e3550000 cmp r5, #0 + 9c: ed9f7a4c vldr s14, [pc, #304] ; 1d4 + a0: ee370a87 vadd.f32 s0, s15, s14 + a4: 0affffe4 beq 3c + a8: eeb10a40 vneg.f32 s0, s0 + ac: e28dd00c add sp, sp, #12 + b0: e8bd8030 pop {r4, r5, pc} + b4: ebfffffe bl 0 + b4: R_ARM_CALL fabsf + b8: e30f3fff movw r3, #65535 ; 0xffff + bc: e3433f97 movt r3, #16279 ; 0x3f97 + c0: e1540003 cmp r4, r3 + c4: e30f3fff movw r3, #65535 ; 0xffff + c8: 8a000012 bhi 118 + cc: e3433f2f movt r3, #16175 ; 0x3f2f + d0: e1540003 cmp r4, r3 + d4: 8a000031 bhi 1a0 + d8: ee307a00 vadd.f32 s14, s0, s0 + dc: eef05a00 vmov.f32 s11, #0 ; 0x40000000 2.0 + e0: eeb76a00 vmov.f32 s12, #112 ; 0x3f800000 1.0 + e4: eddf6a3b vldr s13, [pc, #236] ; 1d8 + e8: ee300a25 vadd.f32 s0, s0, s11 + ec: eddf7a3a vldr s15, [pc, #232] ; 1dc + f0: ee377a46 vsub.f32 s14, s14, s12 + f4: eec75a00 vdiv.f32 s11, s14, s0 + f8: ea00000d b 134 + fc: e3a02000 mov r2, #0 + 100: e3472f80 movt r2, #32640 ; 0x7f80 + 104: e0022003 and r2, r2, r3 + 108: e3520000 cmp r2, #0 + 10c: 0e207a00 vmuleq.f32 s14, s0, s0 + 110: 0d8d7a01 vstreq s14, [sp, #4] + 114: eaffffc7 b 38 + 118: e344301b movt r3, #16411 ; 0x401b + 11c: e1540003 cmp r4, r3 + 120: 9a000016 bls 180 + 124: eebf7a00 vmov.f32 s14, #240 ; 0xbf800000 -1.0 + 128: eddf6a2c vldr s13, [pc, #176] ; 1e0 + 12c: eddf7a27 vldr s15, [pc, #156] ; 1d0 + 130: eec75a00 vdiv.f32 s11, s14, s0 + 134: ee255aa5 vmul.f32 s10, s11, s11 + 138: ed9f3a1f vldr s6, [pc, #124] ; 1bc + 13c: ed9f4a1f vldr s8, [pc, #124] ; 1c0 + 140: e3550000 cmp r5, #0 + 144: eddf3a1e vldr s7, [pc, #120] ; 1c4 + 148: ed9f7a1e vldr s14, [pc, #120] ; 1c8 + 14c: ee256a05 vmul.f32 s12, s10, s10 + 150: eddf4a1d vldr s9, [pc, #116] ; 1cc + 154: ee064a03 vmla.f32 s8, s12, s6 + 158: ee167a23 vnmls.f32 s14, s12, s7 + 15c: ee444a06 vmla.f32 s9, s8, s12 + 160: ee277a06 vmul.f32 s14, s14, s12 + 164: ee047a85 vmla.f32 s14, s9, s10 + 168: ee576a25 vnmls.f32 s13, s14, s11 + 16c: ee367ae5 vsub.f32 s14, s13, s11 + 170: ee370ac7 vsub.f32 s0, s15, s14 + 174: 0affffb0 beq 3c + 178: eeb10a40 vneg.f32 s0, s0 + 17c: eaffffca b ac + 180: eeb76a08 vmov.f32 s12, #120 ; 0x3fc00000 1.5 + 184: eeb77a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 + 188: eddf6a15 vldr s13, [pc, #84] ; 1e4 + 18c: ee007a06 vmla.f32 s14, s0, s12 + 190: ee300a46 vsub.f32 s0, s0, s12 + 194: eddf7a13 vldr s15, [pc, #76] ; 1e8 + 198: eec05a07 vdiv.f32 s11, s0, s14 + 19c: eaffffe4 b 134 + 1a0: eeb77a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 + 1a4: eddf6a10 vldr s13, [pc, #64] ; 1ec + 1a8: eddf7a10 vldr s15, [pc, #64] ; 1f0 + 1ac: ee306a47 vsub.f32 s12, s0, s14 + 1b0: ee300a07 vadd.f32 s0, s0, s14 + 1b4: eec65a00 vdiv.f32 s11, s12, s0 + 1b8: eaffffdd b 134 + 1bc: 3d7cac25 .word 0x3d7cac25 + 1c0: 3e11f50d .word 0x3e11f50d + 1c4: bdda1247 .word 0xbdda1247 + 1c8: 3e4cca98 .word 0x3e4cca98 + 1cc: 3eaaaaa9 .word 0x3eaaaaa9 + 1d0: 3fc90fda .word 0x3fc90fda + 1d4: 03800000 .word 0x03800000 + 1d8: 31ac3769 .word 0x31ac3769 + 1dc: 3eed6338 .word 0x3eed6338 + 1e0: 33a22168 .word 0x33a22168 + 1e4: 33140fb4 .word 0x33140fb4 + 1e8: 3f7b985e .word 0x3f7b985e + 1ec: 33222168 .word 0x33222168 + 1f0: 3f490fda .word 0x3f490fda + +Disassembly of section .text.cosf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e3001fda movw r1, #4058 ; 0xfda + c: e3431f49 movt r1, #16201 ; 0x3f49 + 10: eef07a40 vmov.f32 s15, s0 + 14: e24dd00c sub sp, sp, #12 + 18: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 1c: e1530001 cmp r3, r1 + 20: 8a000007 bhi 44 + 24: e35305e6 cmp r3, #964689920 ; 0x39800000 + 28: 2a000026 bcs c8 + 2c: ed9f7a55 vldr s14, [pc, #340] ; 188 + 30: eeb70a00 vmov.f32 s0, #112 ; 0x3f800000 1.0 + 34: ee777a87 vadd.f32 s15, s15, s14 + 38: edcd7a00 vstr s15, [sp] + 3c: e28dd00c add sp, sp, #12 + 40: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 44: e30513d1 movw r1, #21457 ; 0x53d1 + 48: e344107b movt r1, #16507 ; 0x407b + 4c: e1a02fa2 lsr r2, r2, #31 + 50: e1530001 cmp r3, r1 + 54: 8a00000b bhi 88 + 58: e30c1be3 movw r1, #52195 ; 0xcbe3 + 5c: e3441016 movt r1, #16406 ; 0x4016 + 60: eeb70ac0 vcvt.f64.f32 d0, s0 + 64: e1530001 cmp r3, r1 + 68: 8a00002b bhi 11c + 6c: eddf0b3d vldr d16, [pc, #244] ; 168 + 70: e3520000 cmp r2, #0 + 74: 1e300b20 vaddne.f64 d0, d0, d16 + 78: 0e300bc0 vsubeq.f64 d0, d16, d0 + 7c: e28dd00c add sp, sp, #12 + 80: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 84: eafffffe b 0 + 84: R_ARM_JUMP24 __sindf + 88: e30311d5 movw r1, #12757 ; 0x31d5 + 8c: e34410e2 movt r1, #16610 ; 0x40e2 + 90: e1530001 cmp r3, r1 + 94: 8a00000f bhi d8 + 98: e30e1ddf movw r1, #60895 ; 0xeddf + 9c: e34410af movt r1, #16559 ; 0x40af + a0: e1530001 cmp r3, r1 + a4: 8a000027 bhi 148 + a8: e3520000 cmp r2, #0 + ac: 1eb10a40 vnegne.f32 s0, s0 + b0: 0eb70ae7 vcvteq.f64.f32 d0, s15 + b4: 1ddf0b2d vldrne d16, [pc, #180] ; 170 + b8: 0ddf0b2c vldreq d16, [pc, #176] ; 170 + bc: 1eb70ac0 vcvtne.f64.f32 d0, s0 + c0: ee300b60 vsub.f64 d0, d0, d16 + c4: eaffffec b 7c + c8: eeb70ac0 vcvt.f64.f32 d0, s0 + cc: e28dd00c add sp, sp, #12 + d0: e49de004 pop {lr} ; (ldr lr, [sp], #4) + d4: eafffffe b 0 + d4: R_ARM_JUMP24 __cosdf + d8: e30f2fff movw r2, #65535 ; 0xffff + dc: e3472f7f movt r2, #32639 ; 0x7f7f + e0: e1530002 cmp r3, r2 + e4: 8e300a40 vsubhi.f32 s0, s0, s0 + e8: 8affffd3 bhi 3c + ec: e1a0000d mov r0, sp + f0: ebfffffe bl 0 + f0: R_ARM_CALL __rem_pio2f + f4: e2000003 and r0, r0, #3 + f8: ed9d0b00 vldr d0, [sp] + fc: e3500001 cmp r0, #1 + 100: 0a00000d beq 13c + 104: e3500002 cmp r0, #2 + 108: 0a000007 beq 12c + 10c: e3500000 cmp r0, #0 + 110: 1a000012 bne 160 + 114: ebfffffe bl 0 + 114: R_ARM_CALL __cosdf + 118: eaffffc7 b 3c + 11c: eddf0b15 vldr d16, [pc, #84] ; 178 + 120: e3520000 cmp r2, #0 + 124: 1e300b20 vaddne.f64 d0, d0, d16 + 128: 0e300b60 vsubeq.f64 d0, d0, d16 + 12c: ebfffffe bl 0 + 12c: R_ARM_CALL __cosdf + 130: eeb10a40 vneg.f32 s0, s0 + 134: e28dd00c add sp, sp, #12 + 138: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 13c: eeb10b40 vneg.f64 d0, d0 + 140: ebfffffe bl 0 + 140: R_ARM_CALL __sindf + 144: eaffffbc b 3c + 148: eeb70ac0 vcvt.f64.f32 d0, s0 + 14c: eddf0b0b vldr d16, [pc, #44] ; 180 + 150: e3520000 cmp r2, #0 + 154: 1e300b20 vaddne.f64 d0, d0, d16 + 158: 0e300b60 vsubeq.f64 d0, d0, d16 + 15c: eaffffda b cc + 160: ebfffffe bl 0 + 160: R_ARM_CALL __sindf + 164: eaffffb4 b 3c + 168: 54442d18 .word 0x54442d18 + 16c: 3ff921fb .word 0x3ff921fb + 170: 7f3321d2 .word 0x7f3321d2 + 174: 4012d97c .word 0x4012d97c + 178: 54442d18 .word 0x54442d18 + 17c: 400921fb .word 0x400921fb + 180: 54442d18 .word 0x54442d18 + 184: 401921fb .word 0x401921fb + 188: 7b800000 .word 0x7b800000 + +Disassembly of section .text.expf: + +00000000 : + 0: ee103a10 vmov r3, s0 + 4: e300142a movw r1, #1066 ; 0x42a + 8: eef70ac0 vcvt.f64.f32 d16, s0 + c: e7ea2a53 ubfx r2, r3, #20, #11 + 10: e1520001 cmp r2, r1 + 14: 8a00001c bhi 8c + 18: e3003000 movw r3, #0 + 18: R_ARM_MOVW_ABS_NC __exp2f_data + 1c: e3403000 movt r3, #0 + 1c: R_ARM_MOVT_ABS __exp2f_data + 20: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + 24: e92d4010 push {r4, lr} + 28: e3a0c000 mov ip, #0 + 2c: edd35b4a vldr d21, [r3, #296] ; 0x128 + 30: edd31b48 vldr d17, [r3, #288] ; 0x120 + 34: edd34b4c vldr d20, [r3, #304] ; 0x130 + 38: ee600ba5 vmul.f64 d16, d16, d21 + 3c: edd32b4e vldr d18, [r3, #312] ; 0x138 + 40: edd33b50 vldr d19, [r3, #320] ; 0x140 + 44: ee317ba0 vadd.f64 d7, d17, d16 + 48: ee771b61 vsub.f64 d17, d7, d17 + 4c: ee172a10 vmov r2, s14 + 50: ee700be1 vsub.f64 d16, d16, d17 + 54: e202e01f and lr, r2, #31 + 58: e083418e add r4, r3, lr, lsl #3 + 5c: e793318e ldr r3, [r3, lr, lsl #3] + 60: ee402ba4 vmla.f64 d18, d16, d20 + 64: ee000ba3 vmla.f64 d0, d16, d19 + 68: ee600ba0 vmul.f64 d16, d16, d16 + 6c: e09c0003 adds r0, ip, r3 + 70: e5943004 ldr r3, [r4, #4] + 74: e0831782 add r1, r3, r2, lsl #15 + 78: ee020ba0 vmla.f64 d0, d18, d16 + 7c: ec410b30 vmov d16, r0, r1 + 80: ee200b20 vmul.f64 d0, d0, d16 + 84: eeb70bc0 vcvt.f32.f64 s0, d0 + 88: e8bd8010 pop {r4, pc} + 8c: e3730502 cmn r3, #8388608 ; 0x800000 + 90: 0a000010 beq d8 + 94: e30037f7 movw r3, #2039 ; 0x7f7 + 98: e1520003 cmp r2, r3 + 9c: 8a00000b bhi d0 + a0: eddf7a0e vldr s15, [pc, #56] ; e0 + a4: eeb40ae7 vcmpe.f32 s0, s15 + a8: eef1fa10 vmrs APSR_nzcv, fpscr + ac: ca000005 bgt c8 + b0: eddf7a0b vldr s15, [pc, #44] ; e4 + b4: eeb40ae7 vcmpe.f32 s0, s15 + b8: eef1fa10 vmrs APSR_nzcv, fpscr + bc: 5affffd5 bpl 18 + c0: e3a00000 mov r0, #0 + c4: eafffffe b 0 + c4: R_ARM_JUMP24 __math_uflowf + c8: e3a00000 mov r0, #0 + cc: eafffffe b 0 + cc: R_ARM_JUMP24 __math_oflowf + d0: ee300a00 vadd.f32 s0, s0, s0 + d4: e12fff1e bx lr + d8: ed9f0a02 vldr s0, [pc, #8] ; e8 + dc: e12fff1e bx lr + e0: 42b17217 .word 0x42b17217 + e4: c2cff1b4 .word 0xc2cff1b4 + e8: 00000000 .word 0x00000000 + +Disassembly of section .text.fabsf: + +00000000 : + 0: eeb00ac0 vabs.f32 s0, s0 + 4: e12fff1e bx lr + +Disassembly of section .text.floor: + +00000000 : + 0: eeb50b40 vcmp.f64 d0, #0.0 + 4: ee102a90 vmov r2, s1 + 8: e3000432 movw r0, #1074 ; 0x432 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: e7ea1a52 ubfx r1, r2, #20, #11 + 14: 03a03001 moveq r3, #1 + 18: 13a03000 movne r3, #0 + 1c: e1510000 cmp r1, r0 + 20: c3833001 orrgt r3, r3, #1 + 24: e3530000 cmp r3, #0 + 28: 112fff1e bxne lr + 2c: e24dd008 sub sp, sp, #8 + 30: eddf1b18 vldr d17, [pc, #96] ; 98 + 34: e3520000 cmp r2, #0 + 38: e30033fe movw r3, #1022 ; 0x3fe + 3c: ba00000d blt 78 + 40: ee700b21 vadd.f64 d16, d0, d17 + 44: e1510003 cmp r1, r3 + 48: ee700be1 vsub.f64 d16, d16, d17 + 4c: ee700bc0 vsub.f64 d16, d16, d0 + 50: dd9f0b12 vldrle d0, [pc, #72] ; a0 + 54: ddcd0b00 vstrle d16, [sp] + 58: da000004 ble 70 + 5c: eef50bc0 vcmpe.f64 d16, #0.0 + 60: ee300b20 vadd.f64 d0, d0, d16 + 64: eef1fa10 vmrs APSR_nzcv, fpscr + 68: cef70b00 vmovgt.f64 d16, #112 ; 0x3f800000 1.0 + 6c: ce300b60 vsubgt.f64 d0, d0, d16 + 70: e28dd008 add sp, sp, #8 + 74: e12fff1e bx lr + 78: ee700b61 vsub.f64 d16, d0, d17 + 7c: e1510003 cmp r1, r3 + 80: ee700ba1 vadd.f64 d16, d16, d17 + 84: ee700bc0 vsub.f64 d16, d16, d0 + 88: debf0b00 vmovle.f64 d0, #240 ; 0xbf800000 -1.0 + 8c: ddcd0b00 vstrle d16, [sp] + 90: cafffff1 bgt 5c + 94: eafffff5 b 70 + 98: 00000000 .word 0x00000000 + 9c: 43300000 .word 0x43300000 + ... + +Disassembly of section .text.floorf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e7e73bd2 ubfx r3, r2, #23, #8 + 8: e243307f sub r3, r3, #127 ; 0x7f + c: e3530016 cmp r3, #22 + 10: c12fff1e bxgt lr + 14: e24dd008 sub sp, sp, #8 + 18: e3530000 cmp r3, #0 + 1c: ba00000d blt 58 + 20: e30f1fff movw r1, #65535 ; 0xffff + 24: e340107f movt r1, #127 ; 0x7f + 28: e1a01351 asr r1, r1, r3 + 2c: e1120001 tst r2, r1 + 30: 0a000006 beq 50 + 34: eddf7a13 vldr s15, [pc, #76] ; 88 + 38: e3520000 cmp r2, #0 + 3c: b0822001 addlt r2, r2, r1 + 40: e1c23001 bic r3, r2, r1 + 44: ee300a27 vadd.f32 s0, s0, s15 + 48: ed8d0a00 vstr s0, [sp] + 4c: ee003a10 vmov s0, r3 + 50: e28dd008 add sp, sp, #8 + 54: e12fff1e bx lr + 58: eddf7a0a vldr s15, [pc, #40] ; 88 + 5c: e3520000 cmp r2, #0 + 60: ee300a27 vadd.f32 s0, s0, s15 + 64: ed8d0a01 vstr s0, [sp, #4] + 68: ad9f0a07 vldrge s0, [pc, #28] ; 8c + 6c: aafffff7 bge 50 + 70: eddf7a06 vldr s15, [pc, #24] ; 90 + 74: e1b02082 lsls r2, r2, #1 + 78: eebf0a00 vmov.f32 s0, #240 ; 0xbf800000 -1.0 + 7c: 0eb00a67 vmoveq.f32 s0, s15 + 80: e28dd008 add sp, sp, #8 + 84: e12fff1e bx lr + 88: 7b800000 .word 0x7b800000 + 8c: 00000000 .word 0x00000000 + 90: 80000000 .word 0x80000000 + +Disassembly of section .text.logf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e35205fe cmp r2, #1065353216 ; 0x3f800000 + 8: 0a000020 beq 90 + c: e2423502 sub r3, r2, #8388608 ; 0x800000 + 10: e353047f cmp r3, #2130706432 ; 0x7f000000 + 14: 2a00001f bcs 98 + 18: e2823103 add r3, r2, #-1073741824 ; 0xc0000000 + 1c: e3001000 movw r1, #0 + 1c: R_ARM_MOVW_ABS_NC __logf_data + 20: e3401000 movt r1, #0 + 20: R_ARM_MOVT_ABS __logf_data + 24: e28338cd add r3, r3, #13434880 ; 0xcd0000 + 28: eef72b00 vmov.f64 d18, #112 ; 0x3f800000 1.0 + 2c: e1a0cba3 lsr ip, r3, #23 + 30: e7e309d3 ubfx r0, r3, #19, #4 + 34: edd15b44 vldr d21, [r1, #272] ; 0x110 + 38: e1a03bc3 asr r3, r3, #23 + 3c: e1a0cb8c lsl ip, ip, #23 + 40: e0810200 add r0, r1, r0, lsl #4 + 44: e042200c sub r2, r2, ip + 48: ee072a90 vmov s15, r2 + 4c: edd13b46 vldr d19, [r1, #280] ; 0x118 + 50: eef71ae7 vcvt.f64.f32 d17, s15 + 54: edd06b00 vldr d22, [r0] + 58: ee073a90 vmov s15, r3 + 5c: edd17b40 vldr d23, [r1, #256] ; 0x100 + 60: edd14b42 vldr d20, [r1, #264] ; 0x108 + 64: eef80be7 vcvt.f64.s32 d16, s15 + 68: ed900b02 vldr d0, [r0, #8] + 6c: ee512ba6 vnmls.f64 d18, d17, d22 + 70: ee000ba7 vmla.f64 d0, d16, d23 + 74: ee621ba2 vmul.f64 d17, d18, d18 + 78: ee423ba5 vmla.f64 d19, d18, d21 + 7c: ee300b22 vadd.f64 d0, d0, d18 + 80: ee413ba4 vmla.f64 d19, d17, d20 + 84: ee030ba1 vmla.f64 d0, d19, d17 + 88: eeb70bc0 vcvt.f32.f64 s0, d0 + 8c: e12fff1e bx lr + 90: ed9f0a13 vldr s0, [pc, #76] ; e4 + 94: e12fff1e bx lr + 98: e1b03082 lsls r3, r2, #1 + 9c: 0a00000e beq dc + a0: e3a01000 mov r1, #0 + a4: e3471f80 movt r1, #32640 ; 0x7f80 + a8: e1520001 cmp r2, r1 + ac: 012fff1e bxeq lr + b0: e35304ff cmp r3, #-16777216 ; 0xff000000 + b4: 33a03000 movcc r3, #0 + b8: 23a03001 movcs r3, #1 + bc: e1933fa2 orrs r3, r3, r2, lsr #31 + c0: 1a000004 bne d8 + c4: ed9f7a07 vldr s14, [pc, #28] ; e8 + c8: ee607a07 vmul.f32 s15, s0, s14 + cc: ee173a90 vmov r3, s15 + d0: e243252e sub r2, r3, #192937984 ; 0xb800000 + d4: eaffffcf b 18 + d8: eafffffe b 0 + d8: R_ARM_JUMP24 __math_invalidf + dc: e3a00001 mov r0, #1 + e0: eafffffe b 0 + e0: R_ARM_JUMP24 __math_divzerof + e4: 00000000 .word 0x00000000 + e8: 4b000000 .word 0x4b000000 + +Disassembly of section .text.powf: + +00000000 : + 0: ee102a90 vmov r2, s1 + 4: ee10ca10 vmov ip, s0 + 8: e92d0030 push {r4, r5} + c: e3e00401 mvn r0, #16777216 ; 0x1000000 + 10: e24dd008 sub sp, sp, #8 + 14: e24c3502 sub r3, ip, #8388608 ; 0x800000 + 18: e1a01082 lsl r1, r2, #1 + 1c: e353047f cmp r3, #2130706432 ; 0x7f000000 + 20: e2413001 sub r3, r1, #1 + 24: 2a000046 bcs 144 + 28: e1530000 cmp r3, r0 + 2c: 33a00000 movcc r0, #0 + 30: 2a00005e bcs 1b0 + 34: e28c2103 add r2, ip, #-1073741824 ; 0xc0000000 + 38: e3001000 movw r1, #0 + 38: R_ARM_MOVW_ABS_NC __powf_log2_data + 3c: e3401000 movt r1, #0 + 3c: R_ARM_MOVT_ABS __powf_log2_data + 40: e28228cd add r2, r2, #13434880 ; 0xcd0000 + 44: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + 48: eef71ae0 vcvt.f64.f32 d17, s1 + 4c: e1a03ba2 lsr r3, r2, #23 + 50: e7e329d2 ubfx r2, r2, #19, #4 + 54: edd16b44 vldr d22, [r1, #272] ; 0x110 + 58: e1a03b83 lsl r3, r3, #23 + 5c: e0812202 add r2, r1, r2, lsl #4 + 60: e04cc003 sub ip, ip, r3 + 64: ee07ca90 vmov s15, ip + 68: edd13b46 vldr d19, [r1, #280] ; 0x118 + 6c: e1a03bc3 asr r3, r3, #23 + 70: eef77ae7 vcvt.f64.f32 d23, s15 + 74: edd29b00 vldr d25, [r2] + 78: ee073a10 vmov s14, r3 + 7c: edd28b02 vldr d24, [r2, #8] + 80: edd15b48 vldr d21, [r1, #288] ; 0x120 + 84: e30830bf movw r3, #32959 ; 0x80bf + 88: eeb87bc7 vcvt.f64.s32 d7, s14 + 8c: edd14b40 vldr d20, [r1, #256] ; 0x100 + 90: ee570ba9 vnmls.f64 d16, d23, d25 + 94: edd12b42 vldr d18, [r1, #264] ; 0x108 + 98: ee377b28 vadd.f64 d7, d7, d24 + 9c: ee403ba6 vmla.f64 d19, d16, d22 + a0: ee007ba5 vmla.f64 d7, d16, d21 + a4: ee402ba4 vmla.f64 d18, d16, d20 + a8: eef07b63 vmov.f64 d23, d19 + ac: ee603ba0 vmul.f64 d19, d16, d16 + b0: ee077ba3 vmla.f64 d7, d23, d19 + b4: ee630ba3 vmul.f64 d16, d19, d19 + b8: ee027ba0 vmla.f64 d7, d18, d16 + bc: ee277b21 vmul.f64 d7, d7, d17 + c0: ee172a90 vmov r2, s15 + c4: e7ef27d2 ubfx r2, r2, #15, #16 + c8: e1520003 cmp r2, r3 + cc: 2a00002c bcs 184 + d0: e3002000 movw r2, #0 + d0: R_ARM_MOVW_ABS_NC __exp2f_data + d4: e3402000 movt r2, #0 + d4: R_ARM_MOVT_ABS __exp2f_data + d8: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + dc: e3a01000 mov r1, #0 + e0: edd20b40 vldr d16, [r2, #256] ; 0x100 + e4: edd23b42 vldr d19, [r2, #264] ; 0x108 + e8: edd21b44 vldr d17, [r2, #272] ; 0x110 + ec: ee376b20 vadd.f64 d6, d7, d16 + f0: edd22b46 vldr d18, [r2, #280] ; 0x118 + f4: ee760b60 vsub.f64 d16, d6, d16 + f8: ee163a10 vmov r3, s12 + fc: ee770b60 vsub.f64 d16, d7, d16 + 100: e0900003 adds r0, r0, r3 + 104: e203301f and r3, r3, #31 + 108: e082c183 add ip, r2, r3, lsl #3 + 10c: ee401ba3 vmla.f64 d17, d16, d19 + 110: ee000ba2 vmla.f64 d0, d16, d18 + 114: ee600ba0 vmul.f64 d16, d16, d16 + 118: e7923183 ldr r3, [r2, r3, lsl #3] + 11c: e0914003 adds r4, r1, r3 + 120: e59c3004 ldr r3, [ip, #4] + 124: e0835780 add r5, r3, r0, lsl #15 + 128: ee010ba0 vmla.f64 d0, d17, d16 + 12c: ec454b30 vmov d16, r4, r5 + 130: ee200b20 vmul.f64 d0, d0, d16 + 134: eeb70bc0 vcvt.f32.f64 s0, d0 + 138: e28dd008 add sp, sp, #8 + 13c: e8bd0030 pop {r4, r5} + 140: e12fff1e bx lr + 144: e1530000 cmp r3, r0 + 148: 2a00003d bcs 244 + 14c: e1a0308c lsl r3, ip, #1 + 150: e2433001 sub r3, r3, #1 + 154: e1530000 cmp r3, r0 + 158: 2a000030 bcs 220 + 15c: e35c0000 cmp ip, #0 + 160: a3a00000 movge r0, #0 + 164: ba000016 blt 1c4 + 168: e35c0502 cmp ip, #8388608 ; 0x800000 + 16c: 3ddf7a5d vldrcc s15, [pc, #372] ; 2e8 + 170: 3e200a27 vmulcc.f32 s0, s0, s15 + 174: 3e103a10 vmovcc r3, s0 + 178: 33c33102 biccc r3, r3, #-2147483648 ; 0x80000000 + 17c: 3243c52e subcc ip, r3, #192937984 ; 0xb800000 + 180: eaffffab b 34 + 184: eddf0b53 vldr d16, [pc, #332] ; 2d8 + 188: eeb47be0 vcmpe.f64 d7, d16 + 18c: eef1fa10 vmrs APSR_nzcv, fpscr + 190: ca00001f bgt 214 + 194: eddf0b51 vldr d16, [pc, #324] ; 2e0 + 198: eeb47be0 vcmpe.f64 d7, d16 + 19c: eef1fa10 vmrs APSR_nzcv, fpscr + 1a0: 8affffca bhi d0 + 1a4: e28dd008 add sp, sp, #8 + 1a8: e8bd0030 pop {r4, r5} + 1ac: eafffffe b 0 + 1ac: R_ARM_JUMP24 __math_uflowf + 1b0: e35c05fe cmp ip, #1065353216 ; 0x3f800000 + 1b4: 13510000 cmpne r1, #0 + 1b8: 1a000038 bne 2a0 + 1bc: eeb70a00 vmov.f32 s0, #112 ; 0x3f800000 1.0 + 1c0: eaffffdc b 138 + 1c4: e7e73bd2 ubfx r3, r2, #23, #8 + 1c8: e353007e cmp r3, #126 ; 0x7e + 1cc: 9a00000d bls 208 + 1d0: e3530096 cmp r3, #150 ; 0x96 + 1d4: 8a000022 bhi 264 + 1d8: e3a01001 mov r1, #1 + 1dc: e2633096 rsb r3, r3, #150 ; 0x96 + 1e0: e1a03311 lsl r3, r1, r3 + 1e4: e2431001 sub r1, r3, #1 + 1e8: e1110002 tst r1, r2 + 1ec: 1a000005 bne 208 + 1f0: e1130002 tst r3, r2 + 1f4: 13a00001 movne r0, #1 + 1f8: 03a00000 moveq r0, #0 + 1fc: e1a00800 lsl r0, r0, #16 + 200: e3ccc102 bic ip, ip, #-2147483648 ; 0x80000000 + 204: eaffffd7 b 168 + 208: e28dd008 add sp, sp, #8 + 20c: e8bd0030 pop {r4, r5} + 210: eafffffe b 0 + 210: R_ARM_JUMP24 __math_invalidf + 214: e28dd008 add sp, sp, #8 + 218: e8bd0030 pop {r4, r5} + 21c: eafffffe b 0 + 21c: R_ARM_JUMP24 __math_oflowf + 220: ee200a00 vmul.f32 s0, s0, s0 + 224: e35c0000 cmp ip, #0 + 228: ba00000f blt 26c + 22c: e3520000 cmp r2, #0 + 230: beb77a00 vmovlt.f32 s14, #112 ; 0x3f800000 1.0 + 234: bec77a00 vdivlt.f32 s15, s14, s0 + 238: bdcd7a01 vstrlt s15, [sp, #4] + 23c: bd9d0a01 vldrlt s0, [sp, #4] + 240: eaffffbc b 138 + 244: e3510000 cmp r1, #0 + 248: 0affffdb beq 1bc + 24c: e1a0308c lsl r3, ip, #1 + 250: e35304ff cmp r3, #-16777216 ; 0xff000000 + 254: 935104ff cmpls r1, #-16777216 ; 0xff000000 + 258: 0a00001b beq 2cc + 25c: ee300a20 vadd.f32 s0, s0, s1 + 260: eaffffb4 b 138 + 264: e3a00000 mov r0, #0 + 268: eaffffe4 b 200 + 26c: e7e73bd2 ubfx r3, r2, #23, #8 + 270: e243107f sub r1, r3, #127 ; 0x7f + 274: e3510017 cmp r1, #23 + 278: 8affffeb bhi 22c + 27c: e3a01001 mov r1, #1 + 280: e2633096 rsb r3, r3, #150 ; 0x96 + 284: e1a03311 lsl r3, r1, r3 + 288: e2431001 sub r1, r3, #1 + 28c: e1110002 tst r1, r2 + 290: 1affffe5 bne 22c + 294: e1130002 tst r3, r2 + 298: 1eb10a40 vnegne.f32 s0, s0 + 29c: eaffffe2 b 22c + 2a0: e35104ff cmp r1, #-16777216 ; 0xff000000 + 2a4: 01a0308c lsleq r3, ip, #1 + 2a8: 1affffeb bne 25c + 2ac: e353047f cmp r3, #2130706432 ; 0x7f000000 + 2b0: e1e02002 mvn r2, r2 + 2b4: 33a03000 movcc r3, #0 + 2b8: 23a03001 movcs r3, #1 + 2bc: e1530fa2 cmp r3, r2, lsr #31 + 2c0: 0e200aa0 vmuleq.f32 s0, s1, s1 + 2c4: 1d9f0a08 vldrne s0, [pc, #32] ; 2ec + 2c8: eaffff9a b 138 + 2cc: e353047f cmp r3, #2130706432 ; 0x7f000000 + 2d0: 1afffff5 bne 2ac + 2d4: eaffffb8 b 1bc + 2d8: ffd1d571 .word 0xffd1d571 + 2dc: 405fffff .word 0x405fffff + 2e0: 00000000 .word 0x00000000 + 2e4: c062c000 .word 0xc062c000 + 2e8: 4b000000 .word 0x4b000000 + 2ec: 00000000 .word 0x00000000 + +Disassembly of section .text.scalbn: + +00000000 : + 0: e3500b01 cmp r0, #1024 ; 0x400 + 4: ba000010 blt 4c + 8: eddf0b26 vldr d16, [pc, #152] ; a8 + c: e30037fe movw r3, #2046 ; 0x7fe + 10: e1500003 cmp r0, r3 + 14: ee200b20 vmul.f64 d0, d0, d16 + 18: da000006 ble 38 + 1c: e2403e7f sub r3, r0, #2032 ; 0x7f0 + 20: ee200b20 vmul.f64 d0, d0, d16 + 24: e243300e sub r3, r3, #14 + 28: e30003ff movw r0, #1023 ; 0x3ff + 2c: e1530000 cmp r3, r0 + 30: d0800003 addle r0, r0, r3 + 34: c0800000 addgt r0, r0, r0 + 38: e3a02000 mov r2, #0 + 3c: e1a03a00 lsl r3, r0, #20 + 40: ec432b30 vmov d16, r2, r3 + 44: ee200b20 vmul.f64 d0, d0, d16 + 48: e12fff1e bx lr + 4c: e30f3c02 movw r3, #64514 ; 0xfc02 + 50: e34f3fff movt r3, #65535 ; 0xffff + 54: e1500003 cmp r0, r3 + 58: a2800fff addge r0, r0, #1020 ; 0x3fc + 5c: a2800003 addge r0, r0, #3 + 60: aafffff4 bge 38 + 64: e2802ff2 add r2, r0, #968 ; 0x3c8 + 68: eddf0b10 vldr d16, [pc, #64] ; b0 + 6c: e2822001 add r2, r2, #1 + 70: e1520003 cmp r2, r3 + 74: a2800d1f addge r0, r0, #1984 ; 0x7c0 + 78: ee200b20 vmul.f64 d0, d0, d16 + 7c: a2800008 addge r0, r0, #8 + 80: aaffffec bge 38 + 84: e2802e79 add r2, r0, #1936 ; 0x790 + 88: ee200b20 vmul.f64 d0, d0, d16 + 8c: e2822002 add r2, r2, #2 + 90: e30003ff movw r0, #1023 ; 0x3ff + 94: e1520003 cmp r2, r3 + 98: a0800002 addge r0, r0, r2 + 9c: b0800003 addlt r0, r0, r3 + a0: eaffffe4 b 38 + a4: e320f000 nop {0} + a8: 00000000 .word 0x00000000 + ac: 7fe00000 .word 0x7fe00000 + b0: 00000000 .word 0x00000000 + b4: 03600000 .word 0x03600000 + +Disassembly of section .text.sinf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e3001fda movw r1, #4058 ; 0xfda + c: e3431f49 movt r1, #16201 ; 0x3f49 + 10: e24dd00c sub sp, sp, #12 + 14: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 18: e1530001 cmp r3, r1 + 1c: 8a00000c bhi 54 + 20: e35305e6 cmp r3, #964689920 ; 0x39800000 + 24: 2a000029 bcs d0 + 28: e3a03000 mov r3, #0 + 2c: e3473f80 movt r3, #32640 ; 0x7f80 + 30: e0033002 and r3, r3, r2 + 34: e3530000 cmp r3, #0 + 38: 0d9f7a5a vldreq s14, [pc, #360] ; 1a8 + 3c: 1d9f7a5a vldrne s14, [pc, #360] ; 1ac + 40: 0e207a07 vmuleq.f32 s14, s0, s14 + 44: 1e307a07 vaddne.f32 s14, s0, s14 + 48: ed8d7a00 vstr s14, [sp] + 4c: e28dd00c add sp, sp, #12 + 50: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 54: e30513d1 movw r1, #21457 ; 0x53d1 + 58: e344107b movt r1, #16507 ; 0x407b + 5c: e1a02fa2 lsr r2, r2, #31 + 60: e1530001 cmp r3, r1 + 64: 8a00000b bhi 98 + 68: e30c1be3 movw r1, #52195 ; 0xcbe3 + 6c: e3441016 movt r1, #16406 ; 0x4016 + 70: eeb70ac0 vcvt.f64.f32 d0, s0 + 74: e1530001 cmp r3, r1 + 78: 8a00002a bhi 128 + 7c: eddf0b41 vldr d16, [pc, #260] ; 188 + 80: e3520000 cmp r2, #0 + 84: 0a00002d beq 140 + 88: ee300b20 vadd.f64 d0, d0, d16 + 8c: ebfffffe bl 0 + 8c: R_ARM_CALL __cosdf + 90: eeb10a40 vneg.f32 s0, s0 + 94: eaffffec b 4c + 98: e30311d5 movw r1, #12757 ; 0x31d5 + 9c: e34410e2 movt r1, #16610 ; 0x40e2 + a0: e1530001 cmp r3, r1 + a4: 8a00000d bhi e0 + a8: e30e1ddf movw r1, #60895 ; 0xeddf + ac: e34410af movt r1, #16559 ; 0x40af + b0: eeb70ac0 vcvt.f64.f32 d0, s0 + b4: e1530001 cmp r3, r1 + b8: 8a00002a bhi 168 + bc: eddf0b33 vldr d16, [pc, #204] ; 190 + c0: e3520000 cmp r2, #0 + c4: 0a000021 beq 150 + c8: ee300b20 vadd.f64 d0, d0, d16 + cc: ea00001c b 144 + d0: eeb70ac0 vcvt.f64.f32 d0, s0 + d4: e28dd00c add sp, sp, #12 + d8: e49de004 pop {lr} ; (ldr lr, [sp], #4) + dc: eafffffe b 0 + dc: R_ARM_JUMP24 __sindf + e0: e30f2fff movw r2, #65535 ; 0xffff + e4: e3472f7f movt r2, #32639 ; 0x7f7f + e8: e1530002 cmp r3, r2 + ec: 8e300a40 vsubhi.f32 s0, s0, s0 + f0: 8affffd5 bhi 4c + f4: e1a0000d mov r0, sp + f8: ebfffffe bl 0 + f8: R_ARM_CALL __rem_pio2f + fc: e2000003 and r0, r0, #3 + 100: ed9d0b00 vldr d0, [sp] + 104: e3500001 cmp r0, #1 + 108: 0a000014 beq 160 + 10c: e3500002 cmp r0, #2 + 110: 0a000019 beq 17c + 114: e3500000 cmp r0, #0 + 118: 0a000018 beq 180 + 11c: ebfffffe bl 0 + 11c: R_ARM_CALL __cosdf + 120: eeb10a40 vneg.f32 s0, s0 + 124: eaffffc8 b 4c + 128: eddf0b1a vldr d16, [pc, #104] ; 198 + 12c: e3520000 cmp r2, #0 + 130: 1e300b20 vaddne.f64 d0, d0, d16 + 134: 0e300b60 vsubeq.f64 d0, d0, d16 + 138: eeb10b40 vneg.f64 d0, d0 + 13c: eaffffe4 b d4 + 140: ee300b60 vsub.f64 d0, d0, d16 + 144: e28dd00c add sp, sp, #12 + 148: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 14c: eafffffe b 0 + 14c: R_ARM_JUMP24 __cosdf + 150: ee300b60 vsub.f64 d0, d0, d16 + 154: ebfffffe bl 0 + 154: R_ARM_CALL __cosdf + 158: eeb10a40 vneg.f32 s0, s0 + 15c: eaffffba b 4c + 160: ebfffffe bl 0 + 160: R_ARM_CALL __cosdf + 164: eaffffb8 b 4c + 168: eddf0b0c vldr d16, [pc, #48] ; 1a0 + 16c: e3520000 cmp r2, #0 + 170: 1e300b20 vaddne.f64 d0, d0, d16 + 174: 0e300b60 vsubeq.f64 d0, d0, d16 + 178: eaffffd5 b d4 + 17c: eeb10b40 vneg.f64 d0, d0 + 180: ebfffffe bl 0 + 180: R_ARM_CALL __sindf + 184: eaffffb0 b 4c + 188: 54442d18 .word 0x54442d18 + 18c: 3ff921fb .word 0x3ff921fb + 190: 7f3321d2 .word 0x7f3321d2 + 194: 4012d97c .word 0x4012d97c + 198: 54442d18 .word 0x54442d18 + 19c: 400921fb .word 0x400921fb + 1a0: 54442d18 .word 0x54442d18 + 1a4: 401921fb .word 0x401921fb + 1a8: 03800000 .word 0x03800000 + 1ac: 7b800000 .word 0x7b800000 + +Disassembly of section .text.sqrt: + +00000000 : + 0: eeb10bc0 vsqrt.f64 d0, d0 + 4: e12fff1e bx lr + +Disassembly of section .text.sqrtf: + +00000000 : + 0: eeb10ac0 vsqrt.f32 s0, s0 + 4: e12fff1e bx lr + +Disassembly of section .text.tanf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e3001fda movw r1, #4058 ; 0xfda + c: e3431f49 movt r1, #16201 ; 0x3f49 + 10: e24dd00c sub sp, sp, #12 + 14: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 18: e1530001 cmp r3, r1 + 1c: 8a00000c bhi 54 + 20: e35305e6 cmp r3, #964689920 ; 0x39800000 + 24: 2a00002a bcs d4 + 28: e3a03000 mov r3, #0 + 2c: e3473f80 movt r3, #32640 ; 0x7f80 + 30: e0033002 and r3, r3, r2 + 34: e3530000 cmp r3, #0 + 38: 0d9f7a48 vldreq s14, [pc, #288] ; 160 + 3c: 1d9f7a48 vldrne s14, [pc, #288] ; 164 + 40: 0e207a07 vmuleq.f32 s14, s0, s14 + 44: 1e307a07 vaddne.f32 s14, s0, s14 + 48: ed8d7a00 vstr s14, [sp] + 4c: e28dd00c add sp, sp, #12 + 50: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 54: e30513d1 movw r1, #21457 ; 0x53d1 + 58: e344107b movt r1, #16507 ; 0x407b + 5c: e1a02fa2 lsr r2, r2, #31 + 60: e1530001 cmp r3, r1 + 64: 8a00000c bhi 9c + 68: e30c1be3 movw r1, #52195 ; 0xcbe3 + 6c: e3441016 movt r1, #16406 ; 0x4016 + 70: eeb70ac0 vcvt.f64.f32 d0, s0 + 74: e1530001 cmp r3, r1 + 78: 8a00001a bhi e8 + 7c: eddf0b2f vldr d16, [pc, #188] ; 140 + 80: e3520000 cmp r2, #0 + 84: 0a000010 beq cc + 88: ee300b20 vadd.f64 d0, d0, d16 + 8c: e3a00001 mov r0, #1 + 90: e28dd00c add sp, sp, #12 + 94: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 98: eafffffe b 0 + 98: R_ARM_JUMP24 __tandf + 9c: e30311d5 movw r1, #12757 ; 0x31d5 + a0: e34410e2 movt r1, #16610 ; 0x40e2 + a4: e1530001 cmp r3, r1 + a8: 8a000013 bhi fc + ac: e30e1ddf movw r1, #60895 ; 0xeddf + b0: e34410af movt r1, #16559 ; 0x40af + b4: eeb70ac0 vcvt.f64.f32 d0, s0 + b8: e1530001 cmp r3, r1 + bc: 8a000019 bhi 128 + c0: eddf0b20 vldr d16, [pc, #128] ; 148 + c4: e3520000 cmp r2, #0 + c8: 1affffee bne 88 + cc: ee300b60 vsub.f64 d0, d0, d16 + d0: eaffffed b 8c + d4: eeb70ac0 vcvt.f64.f32 d0, s0 + d8: e3a00000 mov r0, #0 + dc: e28dd00c add sp, sp, #12 + e0: e49de004 pop {lr} ; (ldr lr, [sp], #4) + e4: eafffffe b 0 + e4: R_ARM_JUMP24 __tandf + e8: eddf0b18 vldr d16, [pc, #96] ; 150 + ec: e3520000 cmp r2, #0 + f0: 0a00000f beq 134 + f4: ee300b20 vadd.f64 d0, d0, d16 + f8: eafffff6 b d8 + fc: e30f2fff movw r2, #65535 ; 0xffff + 100: e3472f7f movt r2, #32639 ; 0x7f7f + 104: e1530002 cmp r3, r2 + 108: 8e300a40 vsubhi.f32 s0, s0, s0 + 10c: 8affffce bhi 4c + 110: e1a0000d mov r0, sp + 114: ebfffffe bl 0 + 114: R_ARM_CALL __rem_pio2f + 118: ed9d0b00 vldr d0, [sp] + 11c: e2000001 and r0, r0, #1 + 120: ebfffffe bl 0 + 120: R_ARM_CALL __tandf + 124: eaffffc8 b 4c + 128: eddf0b0a vldr d16, [pc, #40] ; 158 + 12c: e3520000 cmp r2, #0 + 130: 1affffef bne f4 + 134: ee300b60 vsub.f64 d0, d0, d16 + 138: eaffffe6 b d8 + 13c: e320f000 nop {0} + 140: 54442d18 .word 0x54442d18 + 144: 3ff921fb .word 0x3ff921fb + 148: 7f3321d2 .word 0x7f3321d2 + 14c: 4012d97c .word 0x4012d97c + 150: 54442d18 .word 0x54442d18 + 154: 400921fb .word 0x400921fb + 158: 54442d18 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zi!~n2A*b5;H1xCLCi)BhmVQ?;zWE4-@H4gWWwqOp@g+=&@X`MPz~Z}>@vXaDh;J1> zOTVibUmEy&gNN)#f1lIh8^-wN%bRfE@Md-^neGA!qfG2(A0a&33JrfZ9D~6+({MrO!rF&MMm79hu5y>G!%R zXBF**oX-MCt?_sja_YRCG!^zkIr&Qqe5f6g{e{ebZ;1z#zIi0^WR z?@Puv4t$+0GNcw?Et6Xcxqrlv3$k`kqh0H{MZev(`f--=jq7Rj*P^uS`V-?zD30*8 zQTP&)4PC8qTL`{A7Ma-(>Pu6|!B@x>@)~-z5WOsb)aoy#)?B0F3dp(J2|?fIEW?NN lqkhqtS-yu`;lD+Qw Date: Fri, 27 Feb 2026 17:58:15 +0100 Subject: [PATCH 11/15] Fixed addend extraction for R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_ABS --- src/pelfy/_main.py | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index 52521ec..e7db9a7 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -575,7 +575,7 @@ class elf_file: if reloc_types and 'A' in reloc_types[relocation_type][2]: name = reloc_types[relocation_type][0] sh = self.sections[reloc_section['sh_info']] - field = self.read_int(r_offset + sh['sh_offset'], 4, True) + field = self.read_int(r_offset + sh['sh_offset'], 4, False) if name in ('R_386_PC32', 'R_386_32', 'R_X86_64_PC32', 'R_X86_64_PLT32', 'R_ARM_REL32', 'R_ARM_ABS32'): return field if name == 'R_ARM_MOVW_ABS_NC': @@ -595,22 +595,15 @@ class elf_file: return _decode_thumb_branch_imm(field, 22) if name in ('R_ARM_THM_JUMP24', 'R_ARM_THM_CALL'): return _decode_thumb_branch_imm(field, 24) - if name == 'R_ARM_THM_MOVW_ABS_NC': - # Extract addend for Thumb MOVW (lower 16 bits) - imm4 = (field >> 16) & 0xF - i = (field >> 26) & 0x1 - imm3 = (field >> 12) & 0x7 - imm8 = (field >> 0) & 0xFF - addend = (i << 11) | (imm4 << 12) | (imm3 << 8) | imm8 - return addend - if name == 'R_ARM_THM_MOVT_ABS': - # Extract addend for Thumb MOVT (upper 16 bits) - imm4 = (field >> 16) & 0xF - i = (field >> 26) & 0x1 - imm3 = (field >> 12) & 0x7 - imm8 = (field >> 0) & 0xFF - addend = ((i << 11) | (imm4 << 12) | (imm3 << 8) | imm8) << 16 - return addend + if name == 'R_ARM_THM_MOVW_ABS_NC' or name == 'R_ARM_THM_MOVT_ABS': + i = (field >> 10) & 1 + imm4 = field & 0xF + imm3 = (field >> 28) & 0x7 + imm8 = (field >> 16) & 0xFF + imm16 = imm8 | (imm3 << 8) | (i << 11) | (imm4 << 12) + if name == 'R_ARM_THM_MOVT_ABS': + return imm16 << 16 + return imm16 if '_THM_' in name: warnings.warn(f'Thumb relocation addend extraction is for {name} not implemented', stacklevel=2) return 0 From 940488b66078580e8628d69461ca3468c9304899 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Fri, 27 Feb 2026 17:58:55 +0100 Subject: [PATCH 12/15] Extended test for ARM thumb relocations and added reference disassembly --- tests/obj/stencils_armv7thumb_O3_THM_MOVW.asm | 4213 +++++++++++++++++ tests/test_thumb_addend.py | 65 + 2 files changed, 4278 insertions(+) create mode 100644 tests/obj/stencils_armv7thumb_O3_THM_MOVW.asm create mode 100644 tests/test_thumb_addend.py diff --git a/tests/obj/stencils_armv7thumb_O3_THM_MOVW.asm b/tests/obj/stencils_armv7thumb_O3_THM_MOVW.asm new file mode 100644 index 0000000..4173be8 --- /dev/null +++ b/tests/obj/stencils_armv7thumb_O3_THM_MOVW.asm @@ -0,0 +1,4213 @@ + +src/copapy/obj/stencils_armv7thumb_O3.o: file format elf32-littlearm +src/copapy/obj/stencils_armv7thumb_O3.o +architecture: arm, flags 0x00000011: +HAS_RELOC, HAS_SYMS +start address 0x00000000 +private flags = 5000000: [Version5 EABI] + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000014c 00000000 00000000 00000034 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .text.auxsub_get_42 00000018 00000000 00000000 00000180 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text.aux_get_42 0000001c 00000000 00000000 00000198 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 3 .text.entry_function_shell 00000018 00000000 00000000 000001b4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 4 .text.cast_float_int_int 00000010 00000000 00000000 000001cc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 5 .text.cast_float_int_float 00000010 00000000 00000000 000001dc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 6 .text.cast_int_float_int 00000010 00000000 00000000 000001ec 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 7 .text.cast_int_float_float 00000010 00000000 00000000 000001fc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 8 .text.get_42_int 00000018 00000000 00000000 0000020c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 9 .text.get_42_float 00000010 00000000 00000000 00000224 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 10 .text.neg_int 00000008 00000000 00000000 00000234 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 11 .text.neg_float 00000008 00000000 00000000 0000023c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 12 .text.sqrt_int 00000034 00000000 00000000 00000244 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 13 .text.sqrt_float 0000002c 00000000 00000000 00000278 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 14 .text.exp_int 00000018 00000000 00000000 000002a4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 15 .text.exp_float 00000010 00000000 00000000 000002bc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 16 .text.log_int 00000018 00000000 00000000 000002cc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 17 .text.log_float 00000010 00000000 00000000 000002e4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 18 .text.sin_int 00000018 00000000 00000000 000002f4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 19 .text.sin_float 00000010 00000000 00000000 0000030c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 20 .text.cos_int 00000018 00000000 00000000 0000031c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 21 .text.cos_float 00000010 00000000 00000000 00000334 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 22 .text.tan_int 00000018 00000000 00000000 00000344 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 23 .text.tan_float 00000010 00000000 00000000 0000035c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 24 .text.asin_int 00000018 00000000 00000000 0000036c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 25 .text.asin_float 00000010 00000000 00000000 00000384 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 26 .text.acos_int 00000018 00000000 00000000 00000394 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 27 .text.acos_float 00000010 00000000 00000000 000003ac 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 28 .text.atan_int 00000018 00000000 00000000 000003bc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 29 .text.atan_float 00000010 00000000 00000000 000003d4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 30 .text.abs_float 00000008 00000000 00000000 000003e4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 31 .text.abs_int 0000000c 00000000 00000000 000003ec 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 32 .text.sign_int 00000010 00000000 00000000 000003f8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 33 .text.sign_float 0000001c 00000000 00000000 00000408 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 34 .text.atan2_int_int 00000028 00000000 00000000 00000424 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 35 .text.atan2_int_float 0000002c 00000000 00000000 0000044c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 36 .text.atan2_float_int 00000020 00000000 00000000 00000478 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 37 .text.atan2_float_float 00000020 00000000 00000000 00000498 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 38 .text.pow_int_int 00000028 00000000 00000000 000004b8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 39 .text.pow_int_float 0000002c 00000000 00000000 000004e0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 40 .text.pow_float_int 00000020 00000000 00000000 0000050c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 41 .text.pow_float_float 00000020 00000000 00000000 0000052c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 42 .text.min_int_int 0000000c 00000000 00000000 0000054c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 43 .text.max_int_int 0000000c 00000000 00000000 00000558 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 44 .text.min_int_float 00000020 00000000 00000000 00000564 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 45 .text.max_int_float 00000020 00000000 00000000 00000584 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 46 .text.min_float_int 0000001c 00000000 00000000 000005a4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 47 .text.max_float_int 0000001c 00000000 00000000 000005c0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 48 .text.min_float_float 00000014 00000000 00000000 000005dc 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 49 .text.max_float_float 00000014 00000000 00000000 000005f0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 50 .text.add_int_int 00000008 00000000 00000000 00000604 2**2 + CONTENTS, ALLOC, LOAD, RELOC, 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ALLOC, LOAD, RELOC, READONLY, CODE + 60 .text.mul_float_int 00000010 00000000 00000000 00000688 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 61 .text.mul_float_float 00000008 00000000 00000000 00000698 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 62 .text.div_int_int 00000020 00000000 00000000 000006a0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 63 .text.div_int_float 00000014 00000000 00000000 000006c0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 64 .text.div_float_int 00000010 00000000 00000000 000006d4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 65 .text.div_float_float 00000008 00000000 00000000 000006e4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 66 .text.floordiv_int_int 00000024 00000000 00000000 000006ec 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 67 .text.floordiv_int_float 0000002c 00000000 00000000 00000710 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 68 .text.floordiv_float_int 00000024 00000000 00000000 0000073c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 69 .text.floordiv_float_float 00000024 00000000 00000000 00000760 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 70 .text.gt_int_int 0000000c 00000000 00000000 00000784 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 71 .text.gt_int_float 0000001c 00000000 00000000 00000790 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 72 .text.gt_float_int 00000024 00000000 00000000 000007ac 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 73 .text.gt_float_float 00000018 00000000 00000000 000007d0 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 74 .text.ge_int_int 0000000c 00000000 00000000 000007e8 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 75 .text.ge_int_float 0000001c 00000000 00000000 000007f4 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 76 .text.ge_float_int 00000024 00000000 00000000 00000810 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 77 .text.ge_float_float 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ALLOC, LOAD, RELOC, READONLY, CODE +111 .text.store_float_reg0_float_float 00000010 00000000 00000000 00000a8c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +112 .text.__cosdf 00000060 00000000 00000000 00000aa0 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +113 .text.__math_divzerof 00000030 00000000 00000000 00000b00 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +114 .text.__math_invalidf 0000000c 00000000 00000000 00000b30 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +115 .text.__math_oflowf 0000000c 00000000 00000000 00000b3c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +116 .text.__math_uflowf 0000000c 00000000 00000000 00000b48 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +117 .text.__math_xflowf 00000024 00000000 00000000 00000b54 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +118 .text.__rem_pio2_large 00000850 00000000 00000000 00000b78 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +119 .text.__rem_pio2f 00000158 00000000 00000000 000013c8 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +120 .text.__sindf 00000058 00000000 00000000 00001520 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +121 .text.__init_ssp 00000054 00000000 00000000 00001578 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +122 .text.__stack_chk_fail 00000008 00000000 00000000 000015cc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE +123 .text.__tandf 00000088 00000000 00000000 000015d8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE +124 .text.acosf 000001a4 00000000 00000000 00001660 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +125 .text.asinf 00000124 00000000 00000000 00001808 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +126 .text.atan2f 000001dc 00000000 00000000 0000192c 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +127 .text.atanf 000001f4 00000000 00000000 00001b08 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +128 .text.cosf 0000018c 00000000 00000000 00001d00 2**3 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE +129 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.text.__tandf 00000000 .text.__tandf +00000000 l d .text.acosf 00000000 .text.acosf +00000000 l d .text.asinf 00000000 .text.asinf +00000000 l d .text.atan2f 00000000 .text.atan2f +00000000 l d .text.atanf 00000000 .text.atanf +00000000 l d .text.cosf 00000000 .text.cosf +00000000 l d .text.expf 00000000 .text.expf +00000000 l d .text.fabsf 00000000 .text.fabsf +00000000 l d .text.floor 00000000 .text.floor +00000000 l d .text.floorf 00000000 .text.floorf +00000000 l d .text.logf 00000000 .text.logf +00000000 l d .text.powf 00000000 .text.powf +00000000 l d .text.scalbn 00000000 .text.scalbn +00000000 l d .text.sinf 00000000 .text.sinf +00000000 l d .text.sqrt 00000000 .text.sqrt +00000000 l d .text.sqrtf 00000000 .text.sqrtf +00000000 l d .text.tanf 00000000 .text.tanf +00000000 l d .rodata.PIo2 00000000 .rodata.PIo2 +00000000 l d .rodata.ipio2 00000000 .rodata.ipio2 +00000000 l d .rodata.init_jk 00000000 .rodata.init_jk +00000000 l d .rodata.CSWTCH.7 00000000 .rodata.CSWTCH.7 +00000000 l d .rodata.__exp2f_data 00000000 .rodata.__exp2f_data +00000000 l d .rodata.__logf_data 00000000 .rodata.__logf_data +00000000 l d .rodata.__powf_log2_data 00000000 .rodata.__powf_log2_data +00000000 l d .data 00000000 .data +00000000 l d .bss 00000000 .bss +00000000 l d .bss.__stack_chk_guard 00000000 .bss.__stack_chk_guard +00000000 l d .comment 00000000 .comment +00000000 l d .note.GNU-stack 00000000 .note.GNU-stack +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l df *ABS* 00000000 stencils.c +00000000 l df *ABS* 00000000 __cosdf.c +00000000 l df *ABS* 00000000 __math_divzerof.c +00000000 l df *ABS* 00000000 __math_invalidf.c +00000000 l df *ABS* 00000000 __math_oflowf.c +00000000 l df *ABS* 00000000 __math_uflowf.c +00000000 l df *ABS* 00000000 __math_xflowf.c +00000000 l df *ABS* 00000000 __rem_pio2_large.c +00000000 l O .rodata.init_jk 00000010 init_jk +00000000 l O .rodata.ipio2 00000108 ipio2 +00000000 l O .rodata.PIo2 00000040 PIo2 +00000000 l df *ABS* 00000000 __rem_pio2f.c +00000000 l df *ABS* 00000000 __sindf.c +00000000 l df *ABS* 00000000 __stack_chk_fail.c +00000000 l df *ABS* 00000000 __tandf.c +00000000 l df *ABS* 00000000 acosf.c +00000000 l df *ABS* 00000000 asinf.c +00000000 l df *ABS* 00000000 atan2f.c +00000000 l O .rodata.CSWTCH.7 0000000c CSWTCH.7 +00000000 l df *ABS* 00000000 atanf.c +00000000 l df *ABS* 00000000 cosf.c +00000000 l df *ABS* 00000000 exp2f_data.c +00000000 l df *ABS* 00000000 expf.c +00000000 l df *ABS* 00000000 fabsf.c +00000000 l df *ABS* 00000000 floor.c +00000000 l df *ABS* 00000000 floorf.c +00000000 l df *ABS* 00000000 logf.c +00000000 l df *ABS* 00000000 logf_data.c +00000000 l df *ABS* 00000000 powf.c +00000000 l df *ABS* 00000000 powf_data.c +00000000 l df *ABS* 00000000 scalbn.c +00000000 l df *ABS* 00000000 sinf.c +00000000 l df *ABS* 00000000 sqrt.c +00000000 l df *ABS* 00000000 sqrtf.c +00000000 l df *ABS* 00000000 tanf.c +00000000 l df *ABS* 00000000 _divsi3.o +00000008 l .text 00000000 .divsi3_skip_div0_test +00000000 l df *ABS* 00000000 _dvmd_tls.o +00000000 g F .text.min_int_float 0000001e min_int_float +00000000 w F .text.__stack_chk_fail 00000008 .hidden __stack_chk_fail_local +00000000 g F .text.load_float_reg0_int_float 00000014 load_float_reg0_int_float +00000000 g F .text.sqrt 00000008 sqrt +00000000 g F .text.load_float_reg1_int_int 00000010 load_float_reg1_int_int +00000000 g F .text.log_int 00000016 log_int +00000000 g F .text.get_42_float 0000000e get_42_float +00000000 g O .rodata.__logf_data 00000120 .hidden __logf_data +00000000 g F .text.exp_int 00000016 exp_int +00000000 g F .text.powf 000002f0 powf +00000000 g F .text.store_int_reg0_int_float 0000000e store_int_reg0_int_float +00000000 g O .bss.__stack_chk_guard 00000004 __stack_chk_guard +00000000 g F .text.store_float_reg0_float_int 00000010 store_float_reg0_float_int +00000000 g F .text.max_int_int 0000000a max_int_int +00000000 g F .text.__rem_pio2f 00000158 .hidden __rem_pio2f +00000000 g F .text.sign_float 0000001a sign_float +00000000 g F .text.store_int_reg0_int_int 0000000e store_int_reg0_int_int +00000000 g F .text.logf 000000ec logf +00000000 g F .text.sqrt_int 00000032 sqrt_int +00000000 g F .text.floor 000000a8 floor +00000000 g F .text.ge_int_float 0000001a ge_int_float +00000000 g F .text.sqrtf 00000008 sqrtf +00000000 g F .text.load_int_reg1_float_int 0000000e load_int_reg1_float_int +00000000 g F .text.abs_float 00000008 abs_float +00000000 g O .rodata.__exp2f_data 00000148 .hidden __exp2f_data +00000000 g F .text.div_int_int 00000020 div_int_int +00000000 *UND* 00000000 result_int_float +00000000 g F .text.sqrt_float 0000002a sqrt_float +00000000 g F .text.__tandf 00000088 .hidden __tandf +00000000 *UND* 00000000 memcpy +00000000 g F .text.__rem_pio2_large 00000850 .hidden __rem_pio2_large +00000000 g F .text.pow_float_int 0000001e pow_float_int +00000000 g F .text.atan2_int_float 0000002a atan2_int_float +00000000 g F .text.load_int_reg0_int_float 0000000e load_int_reg0_int_float +00000000 g F .text.add_float_int 00000010 add_float_int +00000000 g F .text.bwor_int_int 00000006 bwor_int_int +00000000 g F .text.tan_int 00000016 tan_int +00000000 g F .text.mul_float_int 00000010 mul_float_int +00000000 g F .text.sub_float_float 00000008 sub_float_float +00000000 g F .text.cast_int_float_int 0000000e cast_int_float_int +00000000 g F .text.ge_int_int 0000000c ge_int_int +00000000 g F .text.__math_xflowf 00000024 .hidden __math_xflowf +00000000 g F .text.__math_invalidf 0000000c .hidden __math_invalidf +00000000 g F .text.fabsf 00000008 fabsf +00000000 g F .text.log_float 0000000e log_float +00000000 g F .text.__stack_chk_fail 00000008 __stack_chk_fail +00000000 g F .text.mul_int_float 00000014 mul_int_float +00000000 g F .text.gt_float_float 00000016 gt_float_float +00000000 g F .text.sub_float_int 00000010 sub_float_int +00000000 g F .text.cosf 0000018c cosf +00000000 g F .text.ne_int_int 0000000a ne_int_int +00000000 g F .text.cast_float_int_int 0000000e cast_float_int_int +00000000 *UND* 00000000 result_float_int +00000000 g F .text.div_int_float 00000014 div_int_float +00000000 g F .text.cast_float_int_float 00000010 cast_float_int_float +00000000 g F .text.sin_float 0000000e sin_float +00000000 g F .text.floordiv_int_int 00000022 floordiv_int_int +00000000 g F .text 00000000 .hidden __aeabi_idiv +00000000 g F .text.tan_float 0000000e tan_float +00000000 g F .text.aux_get_42 0000001c aux_get_42 +00000000 g F .text.store_float_reg0_float_float 00000010 store_float_reg0_float_float +00000000 g F .text.__math_uflowf 0000000c .hidden __math_uflowf +00000000 g F .text.gt_int_int 0000000c gt_int_int +00000000 g F .text.mul_float_float 00000008 mul_float_float +00000000 g F .text.load_int_reg0_int_int 0000000e load_int_reg0_int_int +00000000 g F .text.load_float_reg0_int_int 00000012 load_float_reg0_int_int +00000000 g F .text.pow_int_int 00000026 pow_int_int +00000000 *UND* 00000000 result_int +00000000 g F .text.eq_int_float 0000001a eq_int_float +00000000 g F .text.floordiv_float_float 00000022 floordiv_float_float +00000000 g F .text.exp_float 0000000e exp_float +00000000 g F .text.__cosdf 00000060 .hidden __cosdf +00000000 g F .text.add_int_float 00000014 add_int_float +00000000 g F .text.neg_int 00000006 neg_int +00000000 g F .text.rshift_int_int 00000006 rshift_int_int +00000000 g F .text.lshift_int_int 00000006 lshift_int_int +00000000 g F .text.acos_float 0000000e acos_float +00000000 g F .text.load_float_reg1_int_float 00000010 load_float_reg1_int_float +00000000 g F .text.ne_float_int 00000022 ne_float_int +00000000 g F .text.atan2_int_int 00000026 atan2_int_int +00000000 g F .text.pow_float_float 0000001e pow_float_float +00000000 g F .text.atan2_float_int 0000001e atan2_float_int +00000000 g F .text.div_float_float 00000008 div_float_float +00000000 g F .text.eq_int_int 0000000c eq_int_int +00000000 g F .text.max_float_int 0000001a max_float_int +00000000 g F .text.load_float_reg0_float_float 00000010 load_float_reg0_float_float +00000000 g F .text.__init_ssp 00000054 .hidden __init_ssp +00000148 w F .text 00000004 .hidden __aeabi_ldiv0 +00000000 g F .text.ne_float_float 00000016 ne_float_float +00000000 *UND* 00000000 result_float +00000000 g F .text.min_float_int 0000001a min_float_int +00000000 g F .text.add_int_int 00000006 add_int_int +00000000 g F .text.gt_float_int 00000022 gt_float_int +00000000 g F .text.get_42_int 00000016 get_42_int +00000000 g F .text.sub_int_int 00000006 sub_int_int +00000000 g F .text.asin_float 0000000e asin_float +00000000 g F .text.bwxor_int_int 00000006 bwxor_int_int +00000000 g F .text.max_int_float 0000001e max_int_float +00000000 g F .text 00000128 .hidden __divsi3 +00000000 g F .text.min_int_int 0000000a min_int_int +00000000 g F .text.div_float_int 00000010 div_float_int +00000000 g F .text.acosf 000001a4 acosf +00000000 g F .text.atan2_float_float 0000001e atan2_float_float +00000000 g F .text.gt_int_float 0000001a gt_int_float +00000000 g F .text.min_float_float 00000012 min_float_float +00000000 g F .text.load_int_reg1_int_int 0000000e load_int_reg1_int_int +00000000 g F .text.add_float_float 00000008 add_float_float +00000000 g F .text.floordiv_int_float 0000002a floordiv_int_float +00000000 g F .text.cos_float 0000000e cos_float +00000000 g F .text.max_float_float 00000012 max_float_float +00000000 g F .text.ne_int_float 0000001a ne_int_float +00000000 g F .text.scalbn 000000b8 scalbn +00000000 g F .text.atan2f 000001dc atan2f +00000000 g F .text.entry_function_shell 00000016 entry_function_shell +00000000 g F .text.load_int_reg1_float_float 0000000e load_int_reg1_float_float +00000000 g F .text.load_float_reg0_float_int 00000010 load_float_reg0_float_int +00000000 g F .text.ge_float_int 00000022 ge_float_int +00000000 *UND* 00000000 result_int_int +00000000 g F .text.sin_int 00000016 sin_int +00000000 g F .text.sinf 000001b0 sinf +00000000 g F .text.bwand_int_int 00000006 bwand_int_int +00000000 g F .text.atan_float 0000000e atan_float +00000000 g F .text.eq_float_float 00000016 eq_float_float +00000000 g F .text.eq_float_int 00000022 eq_float_int +00000000 g F .text.tanf 00000168 tanf +00000000 g F .text.load_float_reg1_float_float 00000010 load_float_reg1_float_float +00000000 g F .text.acos_int 00000016 acos_int +00000000 g F .text.ge_float_float 00000016 ge_float_float +00000000 g F .text.__math_divzerof 00000030 .hidden __math_divzerof +00000000 g F .text.asin_int 00000016 asin_int +00000000 g F .text.cast_int_float_float 00000010 cast_int_float_float +00000000 g F .text.mod_int_int 00000014 mod_int_int +00000000 g F .text.atanf 000001f4 atanf +00000148 w F .text 00000004 .hidden __aeabi_idiv0 +00000000 g F .text.load_int_reg1_int_float 0000000e load_int_reg1_int_float +00000000 *UND* 00000000 dummy_int +00000000 *UND* 00000000 result_float_float +00000000 g F .text.expf 000000ec expf +00000000 g F .text.__math_oflowf 0000000c .hidden __math_oflowf +00000000 g F .text.floordiv_float_int 00000022 floordiv_float_int +00000000 g F .text.sign_int 00000010 sign_int +00000000 g F .text.sub_int_float 00000014 sub_int_float +00000000 g F .text.cos_int 00000016 cos_int +00000000 *UND* 00000000 dummy_float +00000000 g F .text.floorf 00000094 floorf +00000000 g F .text.neg_float 00000008 neg_float +00000000 g F .text.abs_int 0000000a abs_int +00000000 g F .text.asinf 00000124 asinf +00000000 g F .text.auxsub_get_42 00000016 auxsub_get_42 +00000000 g O .rodata.__powf_log2_data 00000128 .hidden __powf_log2_data +00000000 g F .text.__sindf 00000058 .hidden __sindf +00000000 g F .text.pow_int_float 0000002a pow_int_float +00000128 g F .text 00000020 .hidden __aeabi_idivmod +00000000 g F .text.load_int_reg0_float_float 00000012 load_int_reg0_float_float +00000000 g F .text.load_int_reg0_float_int 00000010 load_int_reg0_float_int +00000000 g F .text.mul_int_int 00000008 mul_int_int +00000000 g F .text.atan_int 00000016 atan_int +00000000 g F .text.load_float_reg1_float_int 00000010 load_float_reg1_float_int + + + +Disassembly of section .text: + +00000000 <__divsi3>: + 0: e3510000 cmp r1, #0 + 4: 0a000043 beq 118 <.divsi3_skip_div0_test+0x110> + +00000008 <.divsi3_skip_div0_test>: + 8: e020c001 eor ip, r0, r1 + c: 42611000 rsbmi r1, r1, #0 + 10: e2512001 subs r2, r1, #1 + 14: 0a000027 beq b8 <.divsi3_skip_div0_test+0xb0> + 18: e1b03000 movs r3, r0 + 1c: 42603000 rsbmi r3, r0, #0 + 20: e1530001 cmp r3, r1 + 24: 9a000026 bls c4 <.divsi3_skip_div0_test+0xbc> + 28: e1110002 tst r1, r2 + 2c: 0a000028 beq d4 <.divsi3_skip_div0_test+0xcc> + 30: e311020e tst r1, #-536870912 ; 0xe0000000 + 34: 01a01181 lsleq r1, r1, #3 + 38: 03a02008 moveq r2, #8 + 3c: 13a02001 movne r2, #1 + 40: e3510201 cmp r1, #268435456 ; 0x10000000 + 44: 31510003 cmpcc r1, r3 + 48: 31a01201 lslcc r1, r1, #4 + 4c: 31a02202 lslcc r2, r2, #4 + 50: 3afffffa bcc 40 <.divsi3_skip_div0_test+0x38> + 54: e3510102 cmp r1, #-2147483648 ; 0x80000000 + 58: 31510003 cmpcc r1, r3 + 5c: 31a01081 lslcc r1, r1, #1 + 60: 31a02082 lslcc r2, r2, #1 + 64: 3afffffa bcc 54 <.divsi3_skip_div0_test+0x4c> + 68: e3a00000 mov r0, #0 + 6c: e1530001 cmp r3, r1 + 70: 20433001 subcs r3, r3, r1 + 74: 21800002 orrcs r0, r0, r2 + 78: e15300a1 cmp r3, r1, lsr #1 + 7c: 204330a1 subcs r3, r3, r1, lsr #1 + 80: 218000a2 orrcs r0, r0, r2, lsr #1 + 84: e1530121 cmp r3, r1, lsr #2 + 88: 20433121 subcs r3, r3, r1, lsr #2 + 8c: 21800122 orrcs r0, r0, r2, lsr #2 + 90: e15301a1 cmp r3, r1, lsr #3 + 94: 204331a1 subcs r3, r3, r1, lsr #3 + 98: 218001a2 orrcs r0, r0, r2, lsr #3 + 9c: e3530000 cmp r3, #0 + a0: 11b02222 lsrsne r2, r2, #4 + a4: 11a01221 lsrne r1, r1, #4 + a8: 1affffef bne 6c <.divsi3_skip_div0_test+0x64> + ac: e35c0000 cmp ip, #0 + b0: 42600000 rsbmi r0, r0, #0 + b4: e12fff1e bx lr + b4: R_ARM_V4BX *ABS* + b8: e13c0000 teq ip, r0 + bc: 42600000 rsbmi r0, r0, #0 + c0: e12fff1e bx lr + c0: R_ARM_V4BX *ABS* + c4: 33a00000 movcc r0, #0 + c8: 01a00fcc asreq r0, ip, #31 + cc: 03800001 orreq r0, r0, #1 + d0: e12fff1e bx lr + d0: R_ARM_V4BX *ABS* + d4: e3510801 cmp r1, #65536 ; 0x10000 + d8: 21a01821 lsrcs r1, r1, #16 + dc: 23a02010 movcs r2, #16 + e0: 33a02000 movcc r2, #0 + e4: e3510c01 cmp r1, #256 ; 0x100 + e8: 21a01421 lsrcs r1, r1, #8 + ec: 22822008 addcs r2, r2, #8 + f0: e3510010 cmp r1, #16 + f4: 21a01221 lsrcs r1, r1, #4 + f8: 22822004 addcs r2, r2, #4 + fc: e3510004 cmp r1, #4 + 100: 82822003 addhi r2, r2, #3 + 104: 908220a1 addls r2, r2, r1, lsr #1 + 108: e35c0000 cmp ip, #0 + 10c: e1a00233 lsr r0, r3, r2 + 110: 42600000 rsbmi r0, r0, #0 + 114: e12fff1e bx lr + 114: R_ARM_V4BX *ABS* + 118: e3500000 cmp r0, #0 + 11c: c3e00102 mvngt r0, #-2147483648 ; 0x80000000 + 120: b3a00102 movlt r0, #-2147483648 ; 0x80000000 + 124: eafffffe b 148 <__aeabi_idiv0> + 124: R_ARM_JUMP24 __aeabi_idiv0 + +00000128 <__aeabi_idivmod>: + 128: e3510000 cmp r1, #0 + 12c: 0afffff9 beq 118 <.divsi3_skip_div0_test+0x110> + 130: e92d4003 push {r0, r1, lr} + 134: ebffffb3 bl 8 <.divsi3_skip_div0_test> + 138: e8bd4006 pop {r1, r2, lr} + 13c: e0030092 mul r3, r2, r0 + 140: e0411003 sub r1, r1, r3 + 144: e12fff1e bx lr + 144: R_ARM_V4BX *ABS* + +00000148 <__aeabi_idiv0>: + 148: e12fff1e bx lr + 148: R_ARM_V4BX *ABS* + +Disassembly of section .text.auxsub_get_42: + +00000000 : + 0: eef1 7a04 vmov.f32 s15, #20 ; 0x40a00000 5.0 + 4: ee07 0a10 vmov s14, r0 + 8: eeb3 0a05 vmov.f32 s0, #53 ; 0x41a80000 21.0 + c: eeb8 7ac7 vcvt.f32.s32 s14, s14 + 10: ee07 0a27 vmla.f32 s0, s14, s15 + 14: 4770 bx lr + 16: bf00 nop + +Disassembly of section .text.aux_get_42: + +00000000 : + 0: eeb0 7a08 vmov.f32 s14, #8 ; 0x40400000 3.0 + 4: eddf 7a04 vldr s15, [pc, #16] ; 18 + 8: ee40 7a07 vmla.f32 s15, s0, s14 + c: eefd 7ae7 vcvt.s32.f32 s15, s15 + 10: ee17 0a90 vmov r0, s15 + 14: f7ff bffe b.w 0 + 14: R_ARM_THM_JUMP24 auxsub_get_42 + 18: 42280000 .word 0x42280000 + +Disassembly of section .text.entry_function_shell: + +00000000 : + 0: b500 push {lr} + 2: b0a1 sub sp, #132 ; 0x84 + 4: 2000 movs r0, #0 + 6: f88d 0000 strb.w r0, [sp] + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL result_int + e: 2001 movs r0, #1 + 10: b021 add sp, #132 ; 0x84 + 12: f85d fb04 ldr.w pc, [sp], #4 + 16: bf00 nop + +Disassembly of section .text.cast_float_int_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: 4608 mov r0, r1 + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float_int + e: bf00 nop + +Disassembly of section .text.cast_float_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.cast_int_float_int: + +00000000 : + 0: eefd 7ac0 vcvt.s32.f32 s15, s0 + 4: 4601 mov r1, r0 + 6: ee17 0a90 vmov r0, s15 + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_int + e: bf00 nop + +Disassembly of section .text.cast_int_float_float: + +00000000 : + 0: eefd 7ac0 vcvt.s32.f32 s15, s0 + 4: eeb0 0a60 vmov.f32 s0, s1 + 8: ee17 0a90 vmov r0, s15 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_int_float + +Disassembly of section .text.get_42_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL aux_get_42 + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.get_42_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL aux_get_42 + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.neg_int: + +00000000 : + 0: 4240 negs r0, r0 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int + 6: bf00 nop + +Disassembly of section .text.neg_float: + +00000000 : + 0: eeb1 0a40 vneg.f32 s0, s0 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_float + +Disassembly of section .text.sqrt_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: ed2d 8b02 vpush {d8} + e: eeb5 0a40 vcmp.f32 s0, #0.0 + 12: eeb1 8ac0 vsqrt.f32 s16, s0 + 16: eef1 fa10 vmrs APSR_nzcv, fpscr + 1a: d407 bmi.n 2c + 1c: eeb0 0a48 vmov.f32 s0, s16 + 20: ecbd 8b02 vpop {d8} + 24: e8bd 4008 ldmia.w sp!, {r3, lr} + 28: f7ff bffe b.w 0 + 28: R_ARM_THM_JUMP24 result_float + 2c: f7ff fffe bl 0 + 2c: R_ARM_THM_CALL sqrtf + 30: e7f4 b.n 1c + 32: bf00 nop + +Disassembly of section .text.sqrt_float: + +00000000 : + 0: eeb5 0a40 vcmp.f32 s0, #0.0 + 4: b508 push {r3, lr} + 6: ed2d 8b02 vpush {d8} + a: eef1 fa10 vmrs APSR_nzcv, fpscr + e: eeb1 8ac0 vsqrt.f32 s16, s0 + 12: d407 bmi.n 24 + 14: eeb0 0a48 vmov.f32 s0, s16 + 18: ecbd 8b02 vpop {d8} + 1c: e8bd 4008 ldmia.w sp!, {r3, lr} + 20: f7ff bffe b.w 0 + 20: R_ARM_THM_JUMP24 result_float + 24: f7ff fffe bl 0 + 24: R_ARM_THM_CALL sqrtf + 28: e7f4 b.n 14 + 2a: bf00 nop + +Disassembly of section .text.exp_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL expf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.exp_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL expf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.log_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL logf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.log_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL logf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.sin_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL sinf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.sin_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL sinf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.cos_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL cosf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.cos_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL cosf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.tan_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL tanf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.tan_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL tanf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.asin_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL asinf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.asin_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL asinf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.acos_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL acosf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.acos_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL acosf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.atan_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL atanf + e: e8bd 4008 ldmia.w sp!, {r3, lr} + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_float + 16: bf00 nop + +Disassembly of section .text.atan_float: + +00000000 : + 0: b508 push {r3, lr} + 2: f7ff fffe bl 0 + 2: R_ARM_THM_CALL atanf + 6: e8bd 4008 ldmia.w sp!, {r3, lr} + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float + e: bf00 nop + +Disassembly of section .text.abs_float: + +00000000 : + 0: eeb0 0ac0 vabs.f32 s0, s0 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_float + +Disassembly of section .text.abs_int: + +00000000 : + 0: 2800 cmp r0, #0 + 2: bfb8 it lt + 4: 4240 neglt r0, r0 + 6: f7ff bffe b.w 0 + 6: R_ARM_THM_JUMP24 result_int + a: bf00 nop + +Disassembly of section .text.sign_int: + +00000000 : + 0: 0fc3 lsrs r3, r0, #31 + 2: 2800 cmp r0, #0 + 4: bfd4 ite le + 6: 4258 negle r0, r3 + 8: f1c3 0001 rsbgt r0, r3, #1 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_int + +Disassembly of section .text.sign_float: + +00000000 : + 0: eeb5 0ac0 vcmpe.f32 s0, #0.0 + 4: eef1 fa10 vmrs APSR_nzcv, fpscr + 8: bfcc ite gt + a: 2001 movgt r0, #1 + c: 2000 movle r0, #0 + e: bf4c ite mi + 10: 2301 movmi r3, #1 + 12: 2300 movpl r3, #0 + 14: 1ac0 subs r0, r0, r3 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_int + 1a: bf00 nop + +Disassembly of section .text.atan2_int_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b500 push {lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: ee07 1a90 vmov s15, r1 + e: b083 sub sp, #12 + 10: 9101 str r1, [sp, #4] + 12: eef8 0ae7 vcvt.f32.s32 s1, s15 + 16: f7ff fffe bl 0 + 16: R_ARM_THM_CALL atan2f + 1a: 9801 ldr r0, [sp, #4] + 1c: b003 add sp, #12 + 1e: f85d eb04 ldr.w lr, [sp], #4 + 22: f7ff bffe b.w 0 + 22: R_ARM_THM_JUMP24 result_float_int + 26: bf00 nop + +Disassembly of section .text.atan2_int_float: + +00000000 : + 0: b508 push {r3, lr} + 2: ee07 0a90 vmov s15, r0 + 6: ed2d 8b02 vpush {d8} + a: eeb0 8a40 vmov.f32 s16, s0 + e: eeb8 0ae7 vcvt.f32.s32 s0, s15 + 12: eef0 0a48 vmov.f32 s1, s16 + 16: f7ff fffe bl 0 + 16: R_ARM_THM_CALL atan2f + 1a: eef0 0a48 vmov.f32 s1, s16 + 1e: ecbd 8b02 vpop {d8} + 22: e8bd 4008 ldmia.w sp!, {r3, lr} + 26: f7ff bffe b.w 0 + 26: R_ARM_THM_JUMP24 result_float_float + 2a: bf00 nop + +Disassembly of section .text.atan2_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b500 push {lr} + 6: b083 sub sp, #12 + 8: eef8 0ae7 vcvt.f32.s32 s1, s15 + c: 9001 str r0, [sp, #4] + e: f7ff fffe bl 0 + e: R_ARM_THM_CALL atan2f + 12: 9801 ldr r0, [sp, #4] + 14: b003 add sp, #12 + 16: f85d eb04 ldr.w lr, [sp], #4 + 1a: f7ff bffe b.w 0 + 1a: R_ARM_THM_JUMP24 result_float_int + 1e: bf00 nop + +Disassembly of section .text.atan2_float_float: + +00000000 : + 0: b508 push {r3, lr} + 2: ed2d 8b02 vpush {d8} + 6: eeb0 8a60 vmov.f32 s16, s1 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL atan2f + e: eef0 0a48 vmov.f32 s1, s16 + 12: ecbd 8b02 vpop {d8} + 16: e8bd 4008 ldmia.w sp!, {r3, lr} + 1a: f7ff bffe b.w 0 + 1a: R_ARM_THM_JUMP24 result_float_float + 1e: bf00 nop + +Disassembly of section .text.pow_int_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b500 push {lr} + 6: eeb8 0ae7 vcvt.f32.s32 s0, s15 + a: ee07 1a90 vmov s15, r1 + e: b083 sub sp, #12 + 10: 9101 str r1, [sp, #4] + 12: eef8 0ae7 vcvt.f32.s32 s1, s15 + 16: f7ff fffe bl 0 + 16: R_ARM_THM_CALL powf + 1a: 9801 ldr r0, [sp, #4] + 1c: b003 add sp, #12 + 1e: f85d eb04 ldr.w lr, [sp], #4 + 22: f7ff bffe b.w 0 + 22: R_ARM_THM_JUMP24 result_float_int + 26: bf00 nop + +Disassembly of section .text.pow_int_float: + +00000000 : + 0: b508 push {r3, lr} + 2: ee07 0a90 vmov s15, r0 + 6: ed2d 8b02 vpush {d8} + a: eeb0 8a40 vmov.f32 s16, s0 + e: eeb8 0ae7 vcvt.f32.s32 s0, s15 + 12: eef0 0a48 vmov.f32 s1, s16 + 16: f7ff fffe bl 0 + 16: R_ARM_THM_CALL powf + 1a: eef0 0a48 vmov.f32 s1, s16 + 1e: ecbd 8b02 vpop {d8} + 22: e8bd 4008 ldmia.w sp!, {r3, lr} + 26: f7ff bffe b.w 0 + 26: R_ARM_THM_JUMP24 result_float_float + 2a: bf00 nop + +Disassembly of section .text.pow_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b500 push {lr} + 6: b083 sub sp, #12 + 8: eef8 0ae7 vcvt.f32.s32 s1, s15 + c: 9001 str r0, [sp, #4] + e: f7ff fffe bl 0 + e: R_ARM_THM_CALL powf + 12: 9801 ldr r0, [sp, #4] + 14: b003 add sp, #12 + 16: f85d eb04 ldr.w lr, [sp], #4 + 1a: f7ff bffe b.w 0 + 1a: R_ARM_THM_JUMP24 result_float_int + 1e: bf00 nop + +Disassembly of section .text.pow_float_float: + +00000000 : + 0: b508 push {r3, lr} + 2: ed2d 8b02 vpush {d8} + 6: eeb0 8a60 vmov.f32 s16, s1 + a: f7ff fffe bl 0 + a: R_ARM_THM_CALL powf + e: eef0 0a48 vmov.f32 s1, s16 + 12: ecbd 8b02 vpop {d8} + 16: e8bd 4008 ldmia.w sp!, {r3, lr} + 1a: f7ff bffe b.w 0 + 1a: R_ARM_THM_JUMP24 result_float_float + 1e: bf00 nop + +Disassembly of section .text.min_int_int: + +00000000 : + 0: 4288 cmp r0, r1 + 2: bfa8 it ge + 4: 4608 movge r0, r1 + 6: f7ff bffe b.w 0 + 6: R_ARM_THM_JUMP24 result_int_int + a: bf00 nop + +Disassembly of section .text.max_int_int: + +00000000 : + 0: 4288 cmp r0, r1 + 2: bfb8 it lt + 4: 4608 movlt r0, r1 + 6: f7ff bffe b.w 0 + 6: R_ARM_THM_JUMP24 result_int_int + a: bf00 nop + +Disassembly of section .text.min_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: eeb4 0ae0 vcmpe.f32 s0, s1 + 10: eef1 fa10 vmrs APSR_nzcv, fpscr + 14: bf58 it pl + 16: eeb0 0a60 vmovpl.f32 s0, s1 + 1a: f7ff bffe b.w 0 + 1a: R_ARM_THM_JUMP24 result_float_float + 1e: bf00 nop + +Disassembly of section .text.max_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: eeb4 0ae0 vcmpe.f32 s0, s1 + 10: eef1 fa10 vmrs APSR_nzcv, fpscr + 14: bfd8 it le + 16: eeb0 0a60 vmovle.f32 s0, s1 + 1a: f7ff bffe b.w 0 + 1a: R_ARM_THM_JUMP24 result_float_float + 1e: bf00 nop + +Disassembly of section .text.min_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: eeb4 0ae7 vcmpe.f32 s0, s15 + c: eef1 fa10 vmrs APSR_nzcv, fpscr + 10: bf58 it pl + 12: eeb0 0a67 vmovpl.f32 s0, s15 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_float_int + 1a: bf00 nop + +Disassembly of section .text.max_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: eeb4 0ae7 vcmpe.f32 s0, s15 + c: eef1 fa10 vmrs APSR_nzcv, fpscr + 10: bfd8 it le + 12: eeb0 0a67 vmovle.f32 s0, s15 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_float_int + 1a: bf00 nop + +Disassembly of section .text.min_float_float: + +00000000 : + 0: eeb4 0ae0 vcmpe.f32 s0, s1 + 4: eef1 fa10 vmrs APSR_nzcv, fpscr + 8: bf58 it pl + a: eeb0 0a60 vmovpl.f32 s0, s1 + e: f7ff bffe b.w 0 + e: R_ARM_THM_JUMP24 result_float_float + 12: bf00 nop + +Disassembly of section .text.max_float_float: + +00000000 : + 0: eeb4 0ae0 vcmpe.f32 s0, s1 + 4: eef1 fa10 vmrs APSR_nzcv, fpscr + 8: bfd8 it le + a: eeb0 0a60 vmovle.f32 s0, s1 + e: f7ff bffe b.w 0 + e: R_ARM_THM_JUMP24 result_float_float + 12: bf00 nop + +Disassembly of section .text.add_int_int: + +00000000 : + 0: 4408 add r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.add_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: ee30 0a20 vadd.f32 s0, s0, s1 + 10: f7ff bffe b.w 0 + 10: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.add_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: ee37 0a80 vadd.f32 s0, s15, s0 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.add_float_float: + +00000000 : + 0: ee30 0a20 vadd.f32 s0, s0, s1 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.sub_int_int: + +00000000 : + 0: 1a40 subs r0, r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.sub_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: ee30 0a60 vsub.f32 s0, s0, s1 + 10: f7ff bffe b.w 0 + 10: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.sub_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: ee30 0a67 vsub.f32 s0, s0, s15 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.sub_float_float: + +00000000 : + 0: ee30 0a60 vsub.f32 s0, s0, s1 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.mul_int_int: + +00000000 : + 0: fb01 f000 mul.w r0, r1, r0 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_int_int + +Disassembly of section .text.mul_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: ee20 0a20 vmul.f32 s0, s0, s1 + 10: f7ff bffe b.w 0 + 10: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.mul_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: ee27 0a80 vmul.f32 s0, s15, s0 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.mul_float_float: + +00000000 : + 0: ee20 0a20 vmul.f32 s0, s0, s1 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.div_int_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b082 sub sp, #8 + 6: 4608 mov r0, r1 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: 9101 str r1, [sp, #4] + e: ee07 1a90 vmov s15, r1 + 12: eef8 7ae7 vcvt.f32.s32 s15, s15 + 16: ee80 0a27 vdiv.f32 s0, s0, s15 + 1a: b002 add sp, #8 + 1c: f7ff bffe b.w 0 + 1c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.div_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef0 0a40 vmov.f32 s1, s0 + 8: eeb8 0ae7 vcvt.f32.s32 s0, s15 + c: ee80 0a20 vdiv.f32 s0, s0, s1 + 10: f7ff bffe b.w 0 + 10: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.div_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: ee80 0a27 vdiv.f32 s0, s0, s15 + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.div_float_float: + +00000000 : + 0: ee80 0a20 vdiv.f32 s0, s0, s1 + 4: f7ff bffe b.w 0 + 4: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.floordiv_int_int: + +00000000 : + 0: b538 push {r3, r4, r5, lr} + 2: 4605 mov r5, r0 + 4: 460c mov r4, r1 + 6: f7ff fffe bl 128 <__aeabi_idivmod> + 6: R_ARM_THM_CALL __aeabi_idivmod + a: b129 cbz r1, 18 + c: 0fe3 lsrs r3, r4, #31 + e: ebb3 7fd5 cmp.w r3, r5, lsr #31 + 12: bf18 it ne + 14: f100 30ff addne.w r0, r0, #4294967295 ; 0xffffffff + 18: 4621 mov r1, r4 + 1a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_int_int + 22: bf00 nop + +Disassembly of section .text.floordiv_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b508 push {r3, lr} + 6: ed2d 8b02 vpush {d8} + a: eeb0 8a40 vmov.f32 s16, s0 + e: eeb8 0ae7 vcvt.f32.s32 s0, s15 + 12: ee80 0a08 vdiv.f32 s0, s0, s16 + 16: f7ff fffe bl 0 + 16: R_ARM_THM_CALL floorf + 1a: eef0 0a48 vmov.f32 s1, s16 + 1e: ecbd 8b02 vpop {d8} + 22: e8bd 4008 ldmia.w sp!, {r3, lr} + 26: f7ff bffe b.w 0 + 26: R_ARM_THM_JUMP24 result_float_float + 2a: bf00 nop + +Disassembly of section .text.floordiv_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b500 push {lr} + 6: eef8 7ae7 vcvt.f32.s32 s15, s15 + a: b083 sub sp, #12 + c: 9001 str r0, [sp, #4] + e: ee80 0a27 vdiv.f32 s0, s0, s15 + 12: f7ff fffe bl 0 + 12: R_ARM_THM_CALL floorf + 16: 9801 ldr r0, [sp, #4] + 18: b003 add sp, #12 + 1a: f85d eb04 ldr.w lr, [sp], #4 + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_float_int + 22: bf00 nop + +Disassembly of section .text.floordiv_float_float: + +00000000 : + 0: b508 push {r3, lr} + 2: ee80 0a20 vdiv.f32 s0, s0, s1 + 6: ed2d 8b02 vpush {d8} + a: eeb0 8a60 vmov.f32 s16, s1 + e: f7ff fffe bl 0 + e: R_ARM_THM_CALL floorf + 12: eef0 0a48 vmov.f32 s1, s16 + 16: ecbd 8b02 vpop {d8} + 1a: e8bd 4008 ldmia.w sp!, {r3, lr} + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_float_float + 22: bf00 nop + +Disassembly of section .text.gt_int_int: + +00000000 : + 0: 4288 cmp r0, r1 + 2: bfd4 ite le + 4: 2000 movle r0, #0 + 6: 2001 movgt r0, #1 + 8: f7ff bffe b.w 0 + 8: R_ARM_THM_JUMP24 result_int_int + +Disassembly of section .text.gt_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: eef4 7ac0 vcmpe.f32 s15, s0 + c: eef1 fa10 vmrs APSR_nzcv, fpscr + 10: bfcc ite gt + 12: 2001 movgt r0, #1 + 14: 2000 movle r0, #0 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_int_float + 1a: bf00 nop + +Disassembly of section .text.gt_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b082 sub sp, #8 + 6: 4601 mov r1, r0 + 8: eef8 7ae7 vcvt.f32.s32 s15, s15 + c: 9001 str r0, [sp, #4] + e: eef4 7ac0 vcmpe.f32 s15, s0 + 12: eef1 fa10 vmrs APSR_nzcv, fpscr + 16: bf4c ite mi + 18: 2001 movmi r0, #1 + 1a: 2000 movpl r0, #0 + 1c: b002 add sp, #8 + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_int_int + 22: bf00 nop + +Disassembly of section .text.gt_float_float: + +00000000 : + 0: eeb4 0ae0 vcmpe.f32 s0, s1 + 4: eeb0 0a60 vmov.f32 s0, s1 + 8: eef1 fa10 vmrs APSR_nzcv, fpscr + c: bfcc ite gt + e: 2001 movgt r0, #1 + 10: 2000 movle r0, #0 + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_int_float + 16: bf00 nop + +Disassembly of section .text.ge_int_int: + +00000000 : + 0: 4288 cmp r0, r1 + 2: bfb4 ite lt + 4: 2000 movlt r0, #0 + 6: 2001 movge r0, #1 + 8: f7ff bffe b.w 0 + 8: R_ARM_THM_JUMP24 result_int_int + +Disassembly of section .text.ge_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: eef4 7ac0 vcmpe.f32 s15, s0 + c: eef1 fa10 vmrs APSR_nzcv, fpscr + 10: bfac ite ge + 12: 2001 movge r0, #1 + 14: 2000 movlt r0, #0 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_int_float + 1a: bf00 nop + +Disassembly of section .text.ge_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b082 sub sp, #8 + 6: 4601 mov r1, r0 + 8: eef8 7ae7 vcvt.f32.s32 s15, s15 + c: 9001 str r0, [sp, #4] + e: eef4 7ac0 vcmpe.f32 s15, s0 + 12: eef1 fa10 vmrs APSR_nzcv, fpscr + 16: bf94 ite ls + 18: 2001 movls r0, #1 + 1a: 2000 movhi r0, #0 + 1c: b002 add sp, #8 + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_int_int + 22: bf00 nop + +Disassembly of section .text.ge_float_float: + +00000000 : + 0: eeb4 0ae0 vcmpe.f32 s0, s1 + 4: eeb0 0a60 vmov.f32 s0, s1 + 8: eef1 fa10 vmrs APSR_nzcv, fpscr + c: bfac ite ge + e: 2001 movge r0, #1 + 10: 2000 movlt r0, #0 + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_int_float + 16: bf00 nop + +Disassembly of section .text.eq_int_int: + +00000000 : + 0: 1a40 subs r0, r0, r1 + 2: fab0 f080 clz r0, r0 + 6: 0940 lsrs r0, r0, #5 + 8: f7ff bffe b.w 0 + 8: R_ARM_THM_JUMP24 result_int_int + +Disassembly of section .text.eq_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: eef4 7a40 vcmp.f32 s15, s0 + c: eef1 fa10 vmrs APSR_nzcv, fpscr + 10: bf0c ite eq + 12: 2001 moveq r0, #1 + 14: 2000 movne r0, #0 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_int_float + 1a: bf00 nop + +Disassembly of section .text.eq_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b082 sub sp, #8 + 6: 4601 mov r1, r0 + 8: eef8 7ae7 vcvt.f32.s32 s15, s15 + c: 9001 str r0, [sp, #4] + e: eef4 7a40 vcmp.f32 s15, s0 + 12: eef1 fa10 vmrs APSR_nzcv, fpscr + 16: bf0c ite eq + 18: 2001 moveq r0, #1 + 1a: 2000 movne r0, #0 + 1c: b002 add sp, #8 + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_int_int + 22: bf00 nop + +Disassembly of section .text.eq_float_float: + +00000000 : + 0: eeb4 0a60 vcmp.f32 s0, s1 + 4: eeb0 0a60 vmov.f32 s0, s1 + 8: eef1 fa10 vmrs APSR_nzcv, fpscr + c: bf0c ite eq + e: 2001 moveq r0, #1 + 10: 2000 movne r0, #0 + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_int_float + 16: bf00 nop + +Disassembly of section .text.ne_int_int: + +00000000 : + 0: 1a40 subs r0, r0, r1 + 2: bf18 it ne + 4: 2001 movne r0, #1 + 6: f7ff bffe b.w 0 + 6: R_ARM_THM_JUMP24 result_int_int + a: bf00 nop + +Disassembly of section .text.ne_int_float: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: eef8 7ae7 vcvt.f32.s32 s15, s15 + 8: eef4 7a40 vcmp.f32 s15, s0 + c: eef1 fa10 vmrs APSR_nzcv, fpscr + 10: bf14 ite ne + 12: 2001 movne r0, #1 + 14: 2000 moveq r0, #0 + 16: f7ff bffe b.w 0 + 16: R_ARM_THM_JUMP24 result_int_float + 1a: bf00 nop + +Disassembly of section .text.ne_float_int: + +00000000 : + 0: ee07 0a90 vmov s15, r0 + 4: b082 sub sp, #8 + 6: 4601 mov r1, r0 + 8: eef8 7ae7 vcvt.f32.s32 s15, s15 + c: 9001 str r0, [sp, #4] + e: eef4 7a40 vcmp.f32 s15, s0 + 12: eef1 fa10 vmrs APSR_nzcv, fpscr + 16: bf14 ite ne + 18: 2001 movne r0, #1 + 1a: 2000 moveq r0, #0 + 1c: b002 add sp, #8 + 1e: f7ff bffe b.w 0 + 1e: R_ARM_THM_JUMP24 result_int_int + 22: bf00 nop + +Disassembly of section .text.ne_float_float: + +00000000 : + 0: eeb4 0a60 vcmp.f32 s0, s1 + 4: eeb0 0a60 vmov.f32 s0, s1 + 8: eef1 fa10 vmrs APSR_nzcv, fpscr + c: bf14 ite ne + e: 2001 movne r0, #1 + 10: 2000 moveq r0, #0 + 12: f7ff bffe b.w 0 + 12: R_ARM_THM_JUMP24 result_int_float + 16: bf00 nop + +Disassembly of section .text.bwand_int_int: + +00000000 : + 0: 4008 ands r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.bwor_int_int: + +00000000 : + 0: 4308 orrs r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.bwxor_int_int: + +00000000 : + 0: 4048 eors r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.lshift_int_int: + +00000000 : + 0: 4088 lsls r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.rshift_int_int: + +00000000 : + 0: 4108 asrs r0, r1 + 2: f7ff bffe b.w 0 + 2: R_ARM_THM_JUMP24 result_int_int + 6: bf00 nop + +Disassembly of section .text.mod_int_int: + +00000000 : + 0: b510 push {r4, lr} + 2: 460c mov r4, r1 + 4: f7ff fffe bl 128 <__aeabi_idivmod> + 4: R_ARM_THM_CALL __aeabi_idivmod + 8: 4608 mov r0, r1 + a: 4621 mov r1, r4 + c: e8bd 4010 ldmia.w sp!, {r4, lr} + 10: f7ff bffe b.w 0 + 10: R_ARM_THM_JUMP24 result_int_int + +Disassembly of section .text.load_int_reg0_int_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6818 ldr r0, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_int + e: bf00 nop + +Disassembly of section .text.load_int_reg1_int_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6819 ldr r1, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_int + e: bf00 nop + +Disassembly of section .text.load_float_reg0_int_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: 4608 mov r0, r1 + a: ed93 0a00 vldr s0, [r3] + e: f7ff bffe b.w 0 + e: R_ARM_THM_JUMP24 result_float_int + 12: bf00 nop + +Disassembly of section .text.load_float_reg1_int_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: ed93 0a00 vldr s0, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_int_float + +Disassembly of section .text.load_int_reg0_int_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6818 ldr r0, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_float + e: bf00 nop + +Disassembly of section .text.load_int_reg1_int_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6819 ldr r1, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_int + e: bf00 nop + +Disassembly of section .text.load_float_reg0_int_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: eef0 0a40 vmov.f32 s1, s0 + c: ed93 0a00 vldr s0, [r3] + 10: f7ff bffe b.w 0 + 10: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.load_float_reg1_int_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: ed93 0a00 vldr s0, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_int_float + +Disassembly of section .text.load_int_reg0_float_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 4601 mov r1, r0 + a: 6818 ldr r0, [r3, #0] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_int_int + +Disassembly of section .text.load_int_reg1_float_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6818 ldr r0, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float_int + e: bf00 nop + +Disassembly of section .text.load_float_reg0_float_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: ed93 0a00 vldr s0, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.load_float_reg1_float_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: edd3 0a00 vldr s1, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.load_int_reg0_float_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: eeb0 0a60 vmov.f32 s0, s1 + c: 6818 ldr r0, [r3, #0] + e: f7ff bffe b.w 0 + e: R_ARM_THM_JUMP24 result_int_float + 12: bf00 nop + +Disassembly of section .text.load_int_reg1_float_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6818 ldr r0, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_float_int + e: bf00 nop + +Disassembly of section .text.load_float_reg0_float_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: ed93 0a00 vldr s0, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.load_float_reg1_float_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: edd3 0a00 vldr s1, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.store_int_reg0_int_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6018 str r0, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_int + e: bf00 nop + +Disassembly of section .text.store_int_reg0_int_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_int + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_int + 8: 6018 str r0, [r3, #0] + a: f7ff bffe b.w 0 + a: R_ARM_THM_JUMP24 result_int_float + e: bf00 nop + +Disassembly of section .text.store_float_reg0_float_int: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: ed83 0a00 vstr s0, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_int + +Disassembly of section .text.store_float_reg0_float_float: + +00000000 : + 0: f240 0300 movw r3, #0 + 0: R_ARM_THM_MOVW_ABS_NC dummy_float + 4: f2c0 0300 movt r3, #0 + 4: R_ARM_THM_MOVT_ABS dummy_float + 8: ed83 0a00 vstr s0, [r3] + c: f7ff bffe b.w 0 + c: R_ARM_THM_JUMP24 result_float_float + +Disassembly of section .text.__cosdf: + +00000000 <__cosdf>: + 0: ee600b00 vmul.f64 d16, d0, d0 + 4: eddf6b0d vldr d22, [pc, #52] ; 40 <__cosdf+0x40> + 8: eef71b00 vmov.f64 d17, #112 ; 0x3f800000 1.0 + c: eddf5b0d vldr d21, [pc, #52] ; 48 <__cosdf+0x48> + 10: eddf2b0e vldr d18, [pc, #56] ; 50 <__cosdf+0x50> + 14: eddf4b0f vldr d20, [pc, #60] ; 58 <__cosdf+0x58> + 18: ee401ba6 vmla.f64 d17, d16, d22 + 1c: ee603ba0 vmul.f64 d19, d16, d16 + 20: ee502ba5 vnmls.f64 d18, d16, d21 + 24: ee600ba3 vmul.f64 d16, d16, d19 + 28: eeb00b61 vmov.f64 d0, d17 + 2c: ee030ba4 vmla.f64 d0, d19, d20 + 30: ee020ba0 vmla.f64 d0, d18, d16 + 34: eeb70bc0 vcvt.f32.f64 s0, d0 + 38: e12fff1e bx lr + 3c: e320f000 nop {0} + 40: fd0c5e81 .word 0xfd0c5e81 + 44: bfdfffff .word 0xbfdfffff + 48: e0ee5069 .word 0xe0ee5069 + 4c: 3ef99342 .word 0x3ef99342 + 50: e80f1e27 .word 0xe80f1e27 + 54: 3f56c087 .word 0x3f56c087 + 58: e1053a42 .word 0xe1053a42 + 5c: 3fa55553 .word 0x3fa55553 + +Disassembly of section .text.__math_divzerof: + +00000000 <__math_divzerof>: + 0: e3500000 cmp r0, #0 + 4: eeff6a00 vmov.f32 s13, #240 ; 0xbf800000 -1.0 + 8: eef77a00 vmov.f32 s15, #112 ; 0x3f800000 1.0 + c: e24dd008 sub sp, sp, #8 + 10: ed9f7a05 vldr s14, [pc, #20] ; 2c <__math_divzerof+0x2c> + 14: 1ef07a66 vmovne.f32 s15, s13 + 18: edcd7a01 vstr s15, [sp, #4] + 1c: ed9d0a01 vldr s0, [sp, #4] + 20: ee800a07 vdiv.f32 s0, s0, s14 + 24: e28dd008 add sp, sp, #8 + 28: e12fff1e bx lr + 2c: 00000000 .word 0x00000000 + +Disassembly of section .text.__math_invalidf: + +00000000 <__math_invalidf>: + 0: ee300a40 vsub.f32 s0, s0, s0 + 4: ee800a00 vdiv.f32 s0, s0, s0 + 8: e12fff1e bx lr + +Disassembly of section .text.__math_oflowf: + +00000000 <__math_oflowf>: + 0: ed9f0a00 vldr s0, [pc] ; 8 <__math_oflowf+0x8> + 4: eafffffe b 0 <__math_oflowf> + 4: R_ARM_JUMP24 __math_xflowf + 8: 70000000 .word 0x70000000 + +Disassembly of section .text.__math_uflowf: + +00000000 <__math_uflowf>: + 0: ed9f0a00 vldr s0, [pc] ; 8 <__math_uflowf+0x8> + 4: eafffffe b 0 <__math_uflowf> + 4: R_ARM_JUMP24 __math_xflowf + 8: 10000000 .word 0x10000000 + +Disassembly of section .text.__math_xflowf: + +00000000 <__math_xflowf>: + 0: e3500000 cmp r0, #0 + 4: e24dd008 sub sp, sp, #8 + 8: 1ef17a40 vnegne.f32 s15, s0 + c: 0ef07a40 vmoveq.f32 s15, s0 + 10: edcd7a01 vstr s15, [sp, #4] + 14: eddd7a01 vldr s15, [sp, #4] + 18: ee200a27 vmul.f32 s0, s0, s15 + 1c: e28dd008 add sp, sp, #8 + 20: e12fff1e bx lr + +Disassembly of section .text.__rem_pio2_large: + +00000000 <__rem_pio2_large>: + 0: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 4: e1a0c003 mov ip, r3 + 8: e1a0a002 mov sl, r2 + c: ed2d8b04 vpush {d8-d9} + 10: e24ddf93 sub sp, sp, #588 ; 0x24c + 14: e3720014 cmn r2, #20 + 18: e3002000 movw r2, #0 + 18: R_ARM_MOVW_ABS_NC init_jk + 1c: e3402000 movt r2, #0 + 1c: R_ARM_MOVT_ABS init_jk + 20: e1a09000 mov r9, r0 + 24: e58d3008 str r3, [sp, #8] + 28: e1a03001 mov r3, r1 + 2c: e59d1280 ldr r1, [sp, #640] ; 0x280 + 30: e24c8001 sub r8, ip, #1 + 34: e7925101 ldr r5, [r2, r1, lsl #2] + 38: ba000189 blt 664 <__rem_pio2_large+0x664> + 3c: e24a2003 sub r2, sl, #3 + 40: e30a1aab movw r1, #43691 ; 0xaaab + 44: e3421aaa movt r1, #10922 ; 0x2aaa + 48: e0c10291 smull r0, r1, r1, r2 + 4c: e1a02fc2 asr r2, r2, #31 + 50: e0622141 rsb r2, r2, r1, asr #2 + 54: e58d2004 str r2, [sp, #4] + 58: e1a01002 mov r1, r2 + 5c: e3e02017 mvn r2, #23 + 60: e0222291 mla r2, r1, r2, r2 + 64: e08aa002 add sl, sl, r2 + 68: e59d2004 ldr r2, [sp, #4] + 6c: e0950008 adds r0, r5, r8 + 70: e0422008 sub r2, r2, r8 + 74: 4a00000e bmi b4 <__rem_pio2_large+0xb4> + 78: e2800001 add r0, r0, #1 + 7c: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 80: e300c000 movw ip, #0 + 80: R_ARM_MOVW_ABS_NC ipio2 + 84: e340c000 movt ip, #0 + 84: R_ARM_MOVT_ABS ipio2 + 88: e0800002 add r0, r0, r2 + 8c: e28d1068 add r1, sp, #104 ; 0x68 + 90: e3520000 cmp r2, #0 + 94: eef00b61 vmov.f64 d16, d17 + 98: a79ce102 ldrge lr, [ip, r2, lsl #2] + 9c: e2822001 add r2, r2, #1 + a0: ae07ea90 vmovge s15, lr + a4: aef80be7 vcvtge.f64.s32 d16, s15 + a8: e1520000 cmp r2, r0 + ac: ece10b02 vstmia r1!, {d16} + b0: 1afffff6 bne 90 <__rem_pio2_large+0x90> + b4: e59d2008 ldr r2, [sp, #8] + b8: e3550000 cmp r5, #0 + bc: e1a04182 lsl r4, r2, #3 + c0: ba00000d blt fc <__rem_pio2_large+0xfc> + c4: e28d0068 add r0, sp, #104 ; 0x68 + c8: f2c00e30 vmov.i64 d16, #0x0000000000000000 + cc: e0800004 add r0, r0, r4 + d0: e28def6a add lr, sp, #424 ; 0x1a8 + d4: e1a0c008 mov ip, r8 + d8: e0856002 add r6, r5, r2 + dc: e0891004 add r1, r9, r4 + e0: e3580000 cmp r8, #0 + e4: aa000081 bge 2f0 <__rem_pio2_large+0x2f0> + e8: e28cc001 add ip, ip, #1 + ec: e2800008 add r0, r0, #8 + f0: e15c0006 cmp ip, r6 + f4: ecee0b02 vstmia lr!, {d16} + f8: 1afffff8 bne e0 <__rem_pio2_large+0xe0> + fc: e2452001 sub r2, r5, #1 + 100: e28d1f92 add r1, sp, #584 ; 0x248 + 104: e1a06105 lsl r6, r5, #2 + 108: e28d7018 add r7, sp, #24 + 10c: e0811102 add r1, r1, r2, lsl #2 + 110: e1a0b005 mov fp, r5 + 114: e2462004 sub r2, r6, #4 + 118: e58d5000 str r5, [sp] + 11c: e0894004 add r4, r9, r4 + 120: e0876006 add r6, r7, r6 + 124: e1a05001 mov r5, r1 + 128: e0872002 add r2, r7, r2 + 12c: e58d3010 str r3, [sp, #16] + 130: e58d200c str r2, [sp, #12] + 134: e1a0318b lsl r3, fp, #3 + 138: e35b0000 cmp fp, #0 + 13c: e08d2003 add r2, sp, r3 + 140: ed920b6a vldr d0, [r2, #424] ; 0x1a8 + 144: da00000f ble 188 <__rem_pio2_large+0x188> + 148: e28d1f6a add r1, sp, #424 ; 0x1a8 + 14c: eddf4bf1 vldr d20, [pc, #964] ; 518 <__rem_pio2_large+0x518> + 150: eddf3bf2 vldr d19, [pc, #968] ; 520 <__rem_pio2_large+0x520> + 154: e0813003 add r3, r1, r3 + 158: e1a02007 mov r2, r7 + 15c: ee600b24 vmul.f64 d16, d0, d20 + 160: eef01b40 vmov.f64 d17, d0 + 164: ed732b02 vldmdb r3!, {d18} + 168: eefd7be0 vcvt.s32.f64 s15, d16 + 16c: e1530001 cmp r3, r1 + 170: eef80be7 vcvt.f64.s32 d16, s15 + 174: ee401be3 vmls.f64 d17, d16, d19 + 178: ee300ba2 vadd.f64 d0, d16, d18 + 17c: eefd7be1 vcvt.s32.f64 s15, d17 + 180: ece27a01 vstmia r2!, {s15} + 184: 1afffff4 bne 15c <__rem_pio2_large+0x15c> + 188: e1a0000a mov r0, sl + 18c: ebfffffe bl 0 <__rem_pio2_large> + 18c: R_ARM_CALL scalbn + 190: eef40b00 vmov.f64 d16, #64 ; 0x3e000000 0.125 + 194: eeb08b40 vmov.f64 d8, d0 + 198: ee200b20 vmul.f64 d0, d0, d16 + 19c: ebfffffe bl 0 <__rem_pio2_large> + 19c: R_ARM_CALL floor + 1a0: eef20b00 vmov.f64 d16, #32 ; 0x41000000 8.0 + 1a4: e35a0000 cmp sl, #0 + 1a8: ee008b60 vmls.f64 d8, d0, d16 + 1ac: eebd9bc8 vcvt.s32.f64 s18, d8 + 1b0: eef80bc9 vcvt.f64.s32 d16, s18 + 1b4: ee388b60 vsub.f64 d8, d8, d16 + 1b8: da000055 ble 314 <__rem_pio2_large+0x314> + 1bc: e24b1001 sub r1, fp, #1 + 1c0: e28d3f92 add r3, sp, #584 ; 0x248 + 1c4: e26a2017 rsb r2, sl, #23 + 1c8: e0831101 add r1, r3, r1, lsl #2 + 1cc: e26a3018 rsb r3, sl, #24 + 1d0: e511c230 ldr ip, [r1, #-560] ; 0xfffffdd0 + 1d4: e1a0035c asr r0, ip, r3 + 1d8: e04c3310 sub r3, ip, r0, lsl r3 + 1dc: ee19ca10 vmov ip, s18 + 1e0: e5013230 str r3, [r1, #-560] ; 0xfffffdd0 + 1e4: e1a02253 asr r2, r3, r2 + 1e8: e3520000 cmp r2, #0 + 1ec: e08c0000 add r0, ip, r0 + 1f0: ee090a10 vmov s18, r0 + 1f4: ca0000f3 bgt 5c8 <__rem_pio2_large+0x5c8> + 1f8: eeb58b40 vcmp.f64 d8, #0.0 + 1fc: eef1fa10 vmrs APSR_nzcv, fpscr + 200: 1a000087 bne 424 <__rem_pio2_large+0x424> + 204: e59d3000 ldr r3, [sp] + 208: e15b0003 cmp fp, r3 + 20c: da000007 ble 230 <__rem_pio2_large+0x230> + 210: e087310b add r3, r7, fp, lsl #2 + 214: e3a01000 mov r1, #0 + 218: e5330004 ldr r0, [r3, #-4]! + 21c: e1811000 orr r1, r1, r0 + 220: e1530006 cmp r3, r6 + 224: 1afffffb bne 218 <__rem_pio2_large+0x218> + 228: e3510000 cmp r1, #0 + 22c: 1a0000f5 bne 608 <__rem_pio2_large+0x608> + 230: e5153230 ldr r3, [r5, #-560] ; 0xfffffdd0 + 234: e28b2001 add r2, fp, #1 + 238: e1a0e002 mov lr, r2 + 23c: e3530000 cmp r3, #0 + 240: 1a0000ee bne 600 <__rem_pio2_large+0x600> + 244: e59d300c ldr r3, [sp, #12] + 248: e3a01001 mov r1, #1 + 24c: e5330004 ldr r0, [r3, #-4]! + 250: e2811001 add r1, r1, #1 + 254: e3500000 cmp r0, #0 + 258: 0afffffb beq 24c <__rem_pio2_large+0x24c> + 25c: e08b1001 add r1, fp, r1 + 260: e59d0008 ldr r0, [sp, #8] + 264: e28dc068 add ip, sp, #104 ; 0x68 + 268: e59d3004 ldr r3, [sp, #4] + 26c: e083300b add r3, r3, fp + 270: e080b00b add fp, r0, fp + 274: e3000000 movw r0, #0 + 274: R_ARM_MOVW_ABS_NC ipio2 + 278: e3400000 movt r0, #0 + 278: R_ARM_MOVT_ABS ipio2 + 27c: e08cc18b add ip, ip, fp, lsl #3 + 280: e28dbf6a add fp, sp, #424 ; 0x1a8 + 284: e08bb182 add fp, fp, r2, lsl #3 + 288: e0800103 add r0, r0, r3, lsl #2 + 28c: e5b03004 ldr r3, [r0, #4]! + 290: e3580000 cmp r8, #0 + 294: ee073a90 vmov s15, r3 + 298: eef80be7 vcvt.f64.s32 d16, s15 + 29c: ecec0b02 vstmia ip!, {d16} + 2a0: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 2a4: ba000006 blt 2c4 <__rem_pio2_large+0x2c4> + 2a8: e1a0200c mov r2, ip + 2ac: e1a03009 mov r3, r9 + 2b0: ecf32b02 vldmia r3!, {d18} + 2b4: ed721b02 vldmdb r2!, {d17} + 2b8: e1530004 cmp r3, r4 + 2bc: ee420ba1 vmla.f64 d16, d18, d17 + 2c0: 1afffffa bne 2b0 <__rem_pio2_large+0x2b0> + 2c4: e28ee001 add lr, lr, #1 + 2c8: eceb0b02 vstmia fp!, {d16} + 2cc: e15e0001 cmp lr, r1 + 2d0: daffffed ble 28c <__rem_pio2_large+0x28c> + 2d4: e1a0b001 mov fp, r1 + 2d8: eaffff95 b 134 <__rem_pio2_large+0x134> + 2dc: e28cc001 add ip, ip, #1 + 2e0: e2800008 add r0, r0, #8 + 2e4: e15c0006 cmp ip, r6 + 2e8: ecee0b02 vstmia lr!, {d16} + 2ec: 0affff82 beq fc <__rem_pio2_large+0xfc> + 2f0: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 2f4: e1a07000 mov r7, r0 + 2f8: e1a02009 mov r2, r9 + 2fc: ecf22b02 vldmia r2!, {d18} + 300: ed771b02 vldmdb r7!, {d17} + 304: e1520001 cmp r2, r1 + 308: ee420ba1 vmla.f64 d16, d18, d17 + 30c: 1afffffa bne 2fc <__rem_pio2_large+0x2fc> + 310: eafffff1 b 2dc <__rem_pio2_large+0x2dc> + 314: 0a00000e beq 354 <__rem_pio2_large+0x354> + 318: eef60b00 vmov.f64 d16, #96 ; 0x3f000000 0.5 + 31c: eeb48be0 vcmpe.f64 d8, d16 + 320: eef1fa10 vmrs APSR_nzcv, fpscr + 324: b3a02000 movlt r2, #0 + 328: baffffb2 blt 1f8 <__rem_pio2_large+0x1f8> + 32c: e35b0000 cmp fp, #0 + 330: ee193a10 vmov r3, s18 + 334: d3a02002 movle r2, #2 + 338: def70b00 vmovle.f64 d16, #112 ; 0x3f800000 1.0 + 33c: e2833001 add r3, r3, #1 + 340: ee093a10 vmov s18, r3 + 344: de308bc8 vsuble.f64 d8, d16, d8 + 348: daffffaa ble 1f8 <__rem_pio2_large+0x1f8> + 34c: e3a02002 mov r2, #2 + 350: ea000009 b 37c <__rem_pio2_large+0x37c> + 354: e08d310b add r3, sp, fp, lsl #2 + 358: e5932014 ldr r2, [r3, #20] + 35c: e1a02bc2 asr r2, r2, #23 + 360: e3520000 cmp r2, #0 + 364: daffffa3 ble 1f8 <__rem_pio2_large+0x1f8> + 368: ee193a10 vmov r3, s18 + 36c: e35b0000 cmp fp, #0 + 370: e2833001 add r3, r3, #1 + 374: ee093a10 vmov s18, r3 + 378: da00009b ble 5ec <__rem_pio2_large+0x5ec> + 37c: e1a03007 mov r3, r7 + 380: e3a00000 mov r0, #0 + 384: e4931004 ldr r1, [r3], #4 + 388: e3510000 cmp r1, #0 + 38c: 0a000089 beq 5b8 <__rem_pio2_large+0x5b8> + 390: e2611401 rsb r1, r1, #16777216 ; 0x1000000 + 394: e3e0c4ff mvn ip, #-16777216 ; 0xff000000 + 398: e5031004 str r1, [r3, #-4] + 39c: ea000002 b 3ac <__rem_pio2_large+0x3ac> + 3a0: e5931000 ldr r1, [r3] + 3a4: e04c1001 sub r1, ip, r1 + 3a8: e4831004 str r1, [r3], #4 + 3ac: e2800001 add r0, r0, #1 + 3b0: e15b0000 cmp fp, r0 + 3b4: cafffff9 bgt 3a0 <__rem_pio2_large+0x3a0> + 3b8: e3a01001 mov r1, #1 + 3bc: e35a0000 cmp sl, #0 + 3c0: da000009 ble 3ec <__rem_pio2_large+0x3ec> + 3c4: e35a0001 cmp sl, #1 + 3c8: 0a00009e beq 648 <__rem_pio2_large+0x648> + 3cc: e35a0002 cmp sl, #2 + 3d0: 1a000005 bne 3ec <__rem_pio2_large+0x3ec> + 3d4: e24b3001 sub r3, fp, #1 + 3d8: e28d0f92 add r0, sp, #584 ; 0x248 + 3dc: e0803103 add r3, r0, r3, lsl #2 + 3e0: e5130230 ldr r0, [r3, #-560] ; 0xfffffdd0 + 3e4: e7f50050 ubfx r0, r0, #0, #22 + 3e8: e5030230 str r0, [r3, #-560] ; 0xfffffdd0 + 3ec: e3520002 cmp r2, #2 + 3f0: 1affff80 bne 1f8 <__rem_pio2_large+0x1f8> + 3f4: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + 3f8: e3510000 cmp r1, #0 + 3fc: ee308b48 vsub.f64 d8, d0, d8 + 400: 0affff7c beq 1f8 <__rem_pio2_large+0x1f8> + 404: e1a0000a mov r0, sl + 408: e58d2014 str r2, [sp, #20] + 40c: ebfffffe bl 0 <__rem_pio2_large> + 40c: R_ARM_CALL scalbn + 410: ee388b40 vsub.f64 d8, d8, d0 + 414: e59d2014 ldr r2, [sp, #20] + 418: eeb58b40 vcmp.f64 d8, #0.0 + 41c: eef1fa10 vmrs APSR_nzcv, fpscr + 420: 0affff77 beq 204 <__rem_pio2_large+0x204> + 424: e59d3010 ldr r3, [sp, #16] + 428: eeb00b48 vmov.f64 d0, d8 + 42c: e26a0000 rsb r0, sl, #0 + 430: e59d5000 ldr r5, [sp] + 434: e58d2004 str r2, [sp, #4] + 438: e58d3000 str r3, [sp] + 43c: ebfffffe bl 0 <__rem_pio2_large> + 43c: R_ARM_CALL scalbn + 440: eddf2b36 vldr d18, [pc, #216] ; 520 <__rem_pio2_large+0x520> + 444: eef00b40 vmov.f64 d16, d0 + 448: e59d3000 ldr r3, [sp] + 44c: e59d2004 ldr r2, [sp, #4] + 450: eeb40be2 vcmpe.f64 d0, d18 + 454: eef1fa10 vmrs APSR_nzcv, fpscr + 458: ba0000d2 blt 7a8 <__rem_pio2_large+0x7a8> + 45c: eddf1b2d vldr d17, [pc, #180] ; 518 <__rem_pio2_large+0x518> + 460: e28b4001 add r4, fp, #1 + 464: e28aa018 add sl, sl, #24 + 468: e08db10b add fp, sp, fp, lsl #2 + 46c: e08d1104 add r1, sp, r4, lsl #2 + 470: ee601b21 vmul.f64 d17, d0, d17 + 474: eebd7be1 vcvt.s32.f64 s14, d17 + 478: eef81bc7 vcvt.f64.s32 d17, s14 + 47c: ee410be2 vmls.f64 d16, d17, d18 + 480: eefd7be0 vcvt.s32.f64 s15, d16 + 484: edcb7a06 vstr s15, [fp, #24] + 488: ed817a06 vstr s14, [r1, #24] + 48c: e1a0000a mov r0, sl + 490: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + 494: e1cd20f0 strd r2, [sp] + 498: ebfffffe bl 0 <__rem_pio2_large> + 498: R_ARM_CALL scalbn + 49c: e1cd20d0 ldrd r2, [sp] + 4a0: e3540000 cmp r4, #0 + 4a4: ba0000ca blt 7d4 <__rem_pio2_large+0x7d4> + 4a8: e284c001 add ip, r4, #1 + 4ac: e28def6a add lr, sp, #424 ; 0x1a8 + 4b0: e0877104 add r7, r7, r4, lsl #2 + 4b4: eddf2b17 vldr d18, [pc, #92] ; 518 <__rem_pio2_large+0x518> + 4b8: e1a0c18c lsl ip, ip, #3 + 4bc: e08e100c add r1, lr, ip + 4c0: e4170004 ldr r0, [r7], #-4 + 4c4: ee070a90 vmov s15, r0 + 4c8: eef80be7 vcvt.f64.s32 d16, s15 + 4cc: ee600b80 vmul.f64 d16, d16, d0 + 4d0: ee200b22 vmul.f64 d0, d0, d18 + 4d4: ed610b02 vstmdb r1!, {d16} + 4d8: e151000e cmp r1, lr + 4dc: 1afffff7 bne 4c0 <__rem_pio2_large+0x4c0> + 4e0: e28d8f42 add r8, sp, #264 ; 0x108 + 4e4: e24c0008 sub r0, ip, #8 + 4e8: e0816000 add r6, r1, r0 + 4ec: e1a09008 mov r9, r8 + 4f0: e1a07004 mov r7, r4 + 4f4: e3a0e000 mov lr, #0 + 4f8: e3550000 cmp r5, #0 + 4fc: ba000075 blt 6d8 <__rem_pio2_large+0x6d8> + 500: e3000000 movw r0, #0 + 500: R_ARM_MOVW_ABS_NC PIo2 + 504: e3400000 movt r0, #0 + 504: R_ARM_MOVT_ABS PIo2 + 508: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 50c: e1a0a006 mov sl, r6 + 510: e3a01000 mov r1, #0 + 514: ea00000a b 544 <__rem_pio2_large+0x544> + 518: 00000000 .word 0x00000000 + 51c: 3e700000 .word 0x3e700000 + 520: 00000000 .word 0x00000000 + 524: 41700000 .word 0x41700000 + ... + 530: ecf02b02 vldmia r0!, {d18} + 534: e1550001 cmp r5, r1 + 538: ecfa1b02 vldmia sl!, {d17} + 53c: ee420ba1 vmla.f64 d16, d18, d17 + 540: ba000002 blt 550 <__rem_pio2_large+0x550> + 544: e151000e cmp r1, lr + 548: e2811001 add r1, r1, #1 + 54c: dafffff7 ble 530 <__rem_pio2_large+0x530> + 550: e2477001 sub r7, r7, #1 + 554: e28ee001 add lr, lr, #1 + 558: e2466008 sub r6, r6, #8 + 55c: e3770001 cmn r7, #1 + 560: ece90b02 vstmia r9!, {d16} + 564: 1affffe3 bne 4f8 <__rem_pio2_large+0x4f8> + 568: e59d1280 ldr r1, [sp, #640] ; 0x280 + 56c: e3510002 cmp r1, #2 + 570: ca00005a bgt 6e0 <__rem_pio2_large+0x6e0> + 574: e3510000 cmp r1, #0 + 578: ca00003d bgt 674 <__rem_pio2_large+0x674> + 57c: 0d5f0b17 vldreq d16, [pc, #-92] ; 528 <__rem_pio2_large+0x528> + 580: 0088c00c addeq ip, r8, ip + 584: 1a000006 bne 5a4 <__rem_pio2_large+0x5a4> + 588: ed7c1b02 vldmdb ip!, {d17} + 58c: ee700ba1 vadd.f64 d16, d16, d17 + 590: e15c0008 cmp ip, r8 + 594: 1afffffb bne 588 <__rem_pio2_large+0x588> + 598: e3520000 cmp r2, #0 + 59c: 1ef10b60 vnegne.f64 d16, d16 + 5a0: edc30b00 vstr d16, [r3] + 5a4: ee193a10 vmov r3, s18 + 5a8: e2030007 and r0, r3, #7 + 5ac: e28ddf93 add sp, sp, #588 ; 0x24c + 5b0: ecbd8b04 vpop {d8-d9} + 5b4: e8bd8ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 5b8: e2800001 add r0, r0, #1 + 5bc: e15b0000 cmp fp, r0 + 5c0: caffff6f bgt 384 <__rem_pio2_large+0x384> + 5c4: eaffff7c b 3bc <__rem_pio2_large+0x3bc> + 5c8: e2800001 add r0, r0, #1 + 5cc: e35b0000 cmp fp, #0 + 5d0: ee090a10 vmov s18, r0 + 5d4: caffff68 bgt 37c <__rem_pio2_large+0x37c> + 5d8: e35a0001 cmp sl, #1 + 5dc: 0a000084 beq 7f4 <__rem_pio2_large+0x7f4> + 5e0: e35a0002 cmp sl, #2 + 5e4: 07f53053 ubfxeq r3, r3, #0, #22 + 5e8: 05013230 streq r3, [r1, #-560] ; 0xfffffdd0 + 5ec: e3520002 cmp r2, #2 + 5f0: 1affff00 bne 1f8 <__rem_pio2_large+0x1f8> + 5f4: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + 5f8: ee308bc8 vsub.f64 d8, d16, d8 + 5fc: eafffefd b 1f8 <__rem_pio2_large+0x1f8> + 600: e1a01002 mov r1, r2 + 604: eaffff15 b 260 <__rem_pio2_large+0x260> + 608: e24b4001 sub r4, fp, #1 + 60c: e59d5000 ldr r5, [sp] + 610: e59d3010 ldr r3, [sp, #16] + 614: e24aa018 sub sl, sl, #24 + 618: e08d1104 add r1, sp, r4, lsl #2 + 61c: e5911018 ldr r1, [r1, #24] + 620: e3510000 cmp r1, #0 + 624: 1affff98 bne 48c <__rem_pio2_large+0x48c> + 628: e24b1107 sub r1, fp, #-1073741823 ; 0xc0000001 + 62c: e0871101 add r1, r7, r1, lsl #2 + 630: e5310004 ldr r0, [r1, #-4]! + 634: e2444001 sub r4, r4, #1 + 638: e24aa018 sub sl, sl, #24 + 63c: e3500000 cmp r0, #0 + 640: 0afffffa beq 630 <__rem_pio2_large+0x630> + 644: eaffff90 b 48c <__rem_pio2_large+0x48c> + 648: e24b3001 sub r3, fp, #1 + 64c: e28d0f92 add r0, sp, #584 ; 0x248 + 650: e0803103 add r3, r0, r3, lsl #2 + 654: e5130230 ldr r0, [r3, #-560] ; 0xfffffdd0 + 658: e7f60050 ubfx r0, r0, #0, #23 + 65c: e5030230 str r0, [r3, #-560] ; 0xfffffdd0 + 660: eaffff61 b 3ec <__rem_pio2_large+0x3ec> + 664: e3a02000 mov r2, #0 + 668: e58d2004 str r2, [sp, #4] + 66c: e3e02017 mvn r2, #23 + 670: eafffe7b b 64 <__rem_pio2_large+0x64> + 674: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 678: eddd0b42 vldr d16, [sp, #264] ; 0x108 + 67c: e088c00c add ip, r8, ip + 680: ed7c2b02 vldmdb ip!, {d18} + 684: ee711ba2 vadd.f64 d17, d17, d18 + 688: e15c0008 cmp ip, r8 + 68c: 1afffffb bne 680 <__rem_pio2_large+0x680> + 690: e3520000 cmp r2, #0 + 694: 1a000048 bne 7bc <__rem_pio2_large+0x7bc> + 698: ee700be1 vsub.f64 d16, d16, d17 + 69c: e3540000 cmp r4, #0 + 6a0: edc31b00 vstr d17, [r3] + 6a4: 0a000009 beq 6d0 <__rem_pio2_large+0x6d0> + 6a8: e28d0e11 add r0, sp, #272 ; 0x110 + 6ac: e3a01001 mov r1, #1 + 6b0: ecf01b02 vldmia r0!, {d17} + 6b4: e2811001 add r1, r1, #1 + 6b8: e1540001 cmp r4, r1 + 6bc: ee700ba1 vadd.f64 d16, d16, d17 + 6c0: aafffffa bge 6b0 <__rem_pio2_large+0x6b0> + 6c4: e3520000 cmp r2, #0 + 6c8: 0a000000 beq 6d0 <__rem_pio2_large+0x6d0> + 6cc: eef10b60 vneg.f64 d16, d16 + 6d0: edc30b02 vstr d16, [r3, #8] + 6d4: eaffffb2 b 5a4 <__rem_pio2_large+0x5a4> + 6d8: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 6dc: eaffff9b b 550 <__rem_pio2_large+0x550> + 6e0: e59d1280 ldr r1, [sp, #640] ; 0x280 + 6e4: e3510003 cmp r1, #3 + 6e8: 1affffad bne 5a4 <__rem_pio2_large+0x5a4> + 6ec: e3540000 cmp r4, #0 + 6f0: 0a000047 beq 814 <__rem_pio2_large+0x814> + 6f4: e1a0c184 lsl ip, r4, #3 + 6f8: e088e00c add lr, r8, ip + 6fc: e1a0100e mov r1, lr + 700: e1a0000e mov r0, lr + 704: edde1b00 vldr d17, [lr] + 708: ed700b02 vldmdb r0!, {d16} + 70c: eef02b61 vmov.f64 d18, d17 + 710: ee711ba0 vadd.f64 d17, d17, d16 + 714: e1500008 cmp r0, r8 + 718: ee700be1 vsub.f64 d16, d16, d17 + 71c: edc01b00 vstr d17, [r0] + 720: ee700ba2 vadd.f64 d16, d16, d18 + 724: edc00b02 vstr d16, [r0, #8] + 728: 1afffff6 bne 708 <__rem_pio2_large+0x708> + 72c: e3540001 cmp r4, #1 + 730: 0a000037 beq 814 <__rem_pio2_large+0x814> + 734: edde1b00 vldr d17, [lr] + 738: e2880008 add r0, r8, #8 + 73c: ed710b02 vldmdb r1!, {d16} + 740: eef02b61 vmov.f64 d18, d17 + 744: ee711ba0 vadd.f64 d17, d17, d16 + 748: e1500001 cmp r0, r1 + 74c: ee700be1 vsub.f64 d16, d16, d17 + 750: edc11b00 vstr d17, [r1] + 754: ee700ba2 vadd.f64 d16, d16, d18 + 758: edc10b02 vstr d16, [r1, #8] + 75c: 1afffff6 bne 73c <__rem_pio2_large+0x73c> + 760: e28c1008 add r1, ip, #8 + 764: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 768: e0881001 add r1, r8, r1 + 76c: e2888010 add r8, r8, #16 + 770: ed711b02 vldmdb r1!, {d17} + 774: ee700ba1 vadd.f64 d16, d16, d17 + 778: e1580001 cmp r8, r1 + 77c: 1afffffb bne 770 <__rem_pio2_large+0x770> + 780: e3520000 cmp r2, #0 + 784: eddd2b42 vldr d18, [sp, #264] ; 0x108 + 788: eddd1b44 vldr d17, [sp, #272] ; 0x110 + 78c: 1ef12b62 vnegne.f64 d18, d18 + 790: 1ef10b60 vnegne.f64 d16, d16 + 794: 1ef11b61 vnegne.f64 d17, d17 + 798: edc32b00 vstr d18, [r3] + 79c: edc31b02 vstr d17, [r3, #8] + 7a0: edc30b04 vstr d16, [r3, #16] + 7a4: eaffff7e b 5a4 <__rem_pio2_large+0x5a4> + 7a8: eefd7bc0 vcvt.s32.f64 s15, d0 + 7ac: e08d110b add r1, sp, fp, lsl #2 + 7b0: e1a0400b mov r4, fp + 7b4: edc17a06 vstr s15, [r1, #24] + 7b8: eaffff33 b 48c <__rem_pio2_large+0x48c> + 7bc: eef12b61 vneg.f64 d18, d17 + 7c0: ee700be1 vsub.f64 d16, d16, d17 + 7c4: e3540000 cmp r4, #0 + 7c8: edc32b00 vstr d18, [r3] + 7cc: 1affffb5 bne 6a8 <__rem_pio2_large+0x6a8> + 7d0: eaffffbd b 6cc <__rem_pio2_large+0x6cc> + 7d4: e59d1280 ldr r1, [sp, #640] ; 0x280 + 7d8: e3510002 cmp r1, #2 + 7dc: ca000009 bgt 808 <__rem_pio2_large+0x808> + 7e0: e3510000 cmp r1, #0 + 7e4: ca00000c bgt 81c <__rem_pio2_large+0x81c> + 7e8: 0d5f0bb2 vldreq d16, [pc, #-712] ; 528 <__rem_pio2_large+0x528> + 7ec: 0affff69 beq 598 <__rem_pio2_large+0x598> + 7f0: eaffff6b b 5a4 <__rem_pio2_large+0x5a4> + 7f4: e7f63053 ubfx r3, r3, #0, #23 + 7f8: e3520002 cmp r2, #2 + 7fc: e5013230 str r3, [r1, #-560] ; 0xfffffdd0 + 800: 1afffe7c bne 1f8 <__rem_pio2_large+0x1f8> + 804: eaffff7a b 5f4 <__rem_pio2_large+0x5f4> + 808: e59d1280 ldr r1, [sp, #640] ; 0x280 + 80c: e3510003 cmp r1, #3 + 810: 1affff63 bne 5a4 <__rem_pio2_large+0x5a4> + 814: f2c00e30 vmov.i64 d16, #0x0000000000000000 + 818: eaffffd8 b 780 <__rem_pio2_large+0x780> + 81c: eddd0b42 vldr d16, [sp, #264] ; 0x108 + 820: e3520000 cmp r2, #0 + 824: 0a000005 beq 840 <__rem_pio2_large+0x840> + 828: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 82c: e3a00000 mov r0, #0 + 830: e3a01102 mov r1, #-2147483648 ; 0x80000000 + 834: e1c300f0 strd r0, [r3] + 838: ee700be1 vsub.f64 d16, d16, d17 + 83c: eaffffa2 b 6cc <__rem_pio2_large+0x6cc> + 840: f2c01e30 vmov.i64 d17, #0x0000000000000000 + 844: ee700be1 vsub.f64 d16, d16, d17 + 848: edc31b00 vstr d17, [r3] + 84c: eaffff9f b 6d0 <__rem_pio2_large+0x6d0> + +Disassembly of section .text.__rem_pio2f: + +00000000 <__rem_pio2f>: + 0: e92d4030 push {r4, r5, lr} + 4: ee105a10 vmov r5, s0 + 8: e3002fda movw r2, #4058 ; 0xfda + c: e3442dc9 movt r2, #19913 ; 0x4dc9 + 10: e24dd01c sub sp, sp, #28 + 14: e1a04000 mov r4, r0 + 18: e3c53102 bic r3, r5, #-2147483648 ; 0x80000000 + 1c: e1530002 cmp r3, r2 + 20: 9a00001c bls 98 <__rem_pio2f+0x98> + 24: e30f2fff movw r2, #65535 ; 0xffff + 28: e3472f7f movt r2, #32639 ; 0x7f7f + 2c: e1530002 cmp r3, r2 + 30: 9a000005 bls 4c <__rem_pio2f+0x4c> + 34: ee300a40 vsub.f32 s0, s0, s0 + 38: e3a00000 mov r0, #0 + 3c: eef70ac0 vcvt.f64.f32 d16, s0 + 40: edc40b00 vstr d16, [r4] + 44: e28dd01c add sp, sp, #28 + 48: e8bd8030 pop {r4, r5, pc} + 4c: e1a02ba3 lsr r2, r3, #23 + 50: e3a01000 mov r1, #0 + 54: e2422096 sub r2, r2, #150 ; 0x96 + 58: e58d1000 str r1, [sp] + 5c: e28d0008 add r0, sp, #8 + 60: e28d1010 add r1, sp, #16 + 64: e0433b82 sub r3, r3, r2, lsl #23 + 68: ee073a90 vmov s15, r3 + 6c: e3a03001 mov r3, #1 + 70: eef70ae7 vcvt.f64.f32 d16, s15 + 74: edcd0b02 vstr d16, [sp, #8] + 78: ebfffffe bl 0 <__rem_pio2f> + 78: R_ARM_CALL __rem_pio2_large + 7c: eddd0b04 vldr d16, [sp, #16] + 80: e3550000 cmp r5, #0 + 84: b2600000 rsblt r0, r0, #0 + 88: bef10b60 vneglt.f64 d16, d16 + 8c: edc40b00 vstr d16, [r4] + 90: e28dd01c add sp, sp, #28 + 94: e8bd8030 pop {r4, r5, pc} + 98: eddf0b22 vldr d16, [pc, #136] ; 128 <__rem_pio2f+0x128> + 9c: eef72ac0 vcvt.f64.f32 d18, s0 + a0: eddf6b22 vldr d22, [pc, #136] ; 130 <__rem_pio2f+0x130> + a4: eddf4b23 vldr d20, [pc, #140] ; 138 <__rem_pio2f+0x138> + a8: eef01b60 vmov.f64 d17, d16 + ac: eddf3b23 vldr d19, [pc, #140] ; 140 <__rem_pio2f+0x140> + b0: ee421ba6 vmla.f64 d17, d18, d22 + b4: eddf5b23 vldr d21, [pc, #140] ; 148 <__rem_pio2f+0x148> + b8: ee711be0 vsub.f64 d17, d17, d16 + bc: eef00b62 vmov.f64 d16, d18 + c0: ee410be4 vmls.f64 d16, d17, d20 + c4: eefd7be1 vcvt.s32.f64 s15, d17 + c8: ee410be3 vmls.f64 d16, d17, d19 + cc: ee170a90 vmov r0, s15 + d0: eef40be5 vcmpe.f64 d16, d21 + d4: eef1fa10 vmrs APSR_nzcv, fpscr + d8: 4a00000a bmi 108 <__rem_pio2f+0x108> + dc: eddf5b1b vldr d21, [pc, #108] ; 150 <__rem_pio2f+0x150> + e0: eef40be5 vcmpe.f64 d16, d21 + e4: eef1fa10 vmrs APSR_nzcv, fpscr + e8: daffffd4 ble 40 <__rem_pio2f+0x40> + ec: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + f0: e2800001 add r0, r0, #1 + f4: ee711ba0 vadd.f64 d17, d17, d16 + f8: ee412be4 vmls.f64 d18, d17, d20 + fc: eef00b62 vmov.f64 d16, d18 + 100: ee410be3 vmls.f64 d16, d17, d19 + 104: eaffffcd b 40 <__rem_pio2f+0x40> + 108: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + 10c: e2400001 sub r0, r0, #1 + 110: ee711be0 vsub.f64 d17, d17, d16 + 114: ee412be4 vmls.f64 d18, d17, d20 + 118: eef00b62 vmov.f64 d16, d18 + 11c: ee410be3 vmls.f64 d16, d17, d19 + 120: eaffffc6 b 40 <__rem_pio2f+0x40> + 124: e320f000 nop {0} + 128: 00000000 .word 0x00000000 + 12c: 43380000 .word 0x43380000 + 130: 6dc9c883 .word 0x6dc9c883 + 134: 3fe45f30 .word 0x3fe45f30 + 138: 50000000 .word 0x50000000 + 13c: 3ff921fb .word 0x3ff921fb + 140: 611a6263 .word 0x611a6263 + 144: 3e5110b4 .word 0x3e5110b4 + 148: 60000000 .word 0x60000000 + 14c: bfe921fb .word 0xbfe921fb + 150: 60000000 .word 0x60000000 + 154: 3fe921fb .word 0x3fe921fb + +Disassembly of section .text.__sindf: + +00000000 <__sindf>: + 0: ee600b00 vmul.f64 d16, d0, d0 + 4: eddf3b0b vldr d19, [pc, #44] ; 38 <__sindf+0x38> + 8: eddf2b0c vldr d18, [pc, #48] ; 40 <__sindf+0x40> + c: eddf4b0d vldr d20, [pc, #52] ; 48 <__sindf+0x48> + 10: eddf1b0e vldr d17, [pc, #56] ; 50 <__sindf+0x50> + 14: ee502ba3 vnmls.f64 d18, d16, d19 + 18: ee603b20 vmul.f64 d19, d0, d16 + 1c: ee501ba4 vnmls.f64 d17, d16, d20 + 20: ee600ba0 vmul.f64 d16, d16, d16 + 24: ee600ba3 vmul.f64 d16, d16, d19 + 28: ee020ba3 vmla.f64 d0, d18, d19 + 2c: ee000ba1 vmla.f64 d0, d16, d17 + 30: eeb70bc0 vcvt.f32.f64 s0, d0 + 34: e12fff1e bx lr + 38: 896efbb2 .word 0x896efbb2 + 3c: 3f811110 .word 0x3f811110 + 40: 54cbac77 .word 0x54cbac77 + 44: 3fc55555 .word 0x3fc55555 + 48: 8c3b46a7 .word 0x8c3b46a7 + 4c: 3ec6cd87 .word 0x3ec6cd87 + 50: e2cae774 .word 0xe2cae774 + 54: 3f2a00f9 .word 0x3f2a00f9 + +Disassembly of section .text.__init_ssp: + +00000000 <__init_ssp>: + 0: e2501000 subs r1, r0, #0 + 4: 0a000009 beq 30 <__init_ssp+0x30> + 8: e92d4010 push {r4, lr} + c: e3004000 movw r4, #0 + c: R_ARM_MOVW_ABS_NC __stack_chk_guard + 10: e3404000 movt r4, #0 + 10: R_ARM_MOVT_ABS __stack_chk_guard + 14: e3a02004 mov r2, #4 + 18: e1a00004 mov r0, r4 + 1c: ebfffffe bl 0 + 1c: R_ARM_CALL memcpy + 20: e5943000 ldr r3, [r4] + 24: ee1d2f70 mrc 15, 0, r2, cr13, cr0, {3} + 28: e5023008 str r3, [r2, #-8] + 2c: e8bd8010 pop {r4, pc} + 30: e3002000 movw r2, #0 + 30: R_ARM_MOVW_ABS_NC __stack_chk_guard + 34: e3402000 movt r2, #0 + 34: R_ARM_MOVT_ABS __stack_chk_guard + 38: e3043e6d movw r3, #20077 ; 0x4e6d + 3c: e34431c6 movt r3, #16838 ; 0x41c6 + 40: e0030293 mul r3, r3, r2 + 44: e5823000 str r3, [r2] + 48: ee1d2f70 mrc 15, 0, r2, cr13, cr0, {3} + 4c: e5023008 str r3, [r2, #-8] + 50: e12fff1e bx lr + +Disassembly of section .text.__stack_chk_fail: + +00000000 <__stack_chk_fail>: + 0: e7f000f0 .word 0xe7f000f0 + 4: e12fff1e bx lr + +Disassembly of section .text.__tandf: + +00000000 <__tandf>: + 0: ee600b00 vmul.f64 d16, d0, d0 + 4: eddf4b13 vldr d20, [pc, #76] ; 58 <__tandf+0x58> + 8: eddf3b14 vldr d19, [pc, #80] ; 60 <__tandf+0x60> + c: e3500000 cmp r0, #0 + 10: eddf6b14 vldr d22, [pc, #80] ; 68 <__tandf+0x68> + 14: eddf5b15 vldr d21, [pc, #84] ; 70 <__tandf+0x70> + 18: ee403ba4 vmla.f64 d19, d16, d20 + 1c: eddf1b15 vldr d17, [pc, #84] ; 78 <__tandf+0x78> + 20: eddf2b16 vldr d18, [pc, #88] ; 80 <__tandf+0x80> + 24: ee604ba0 vmul.f64 d20, d16, d16 + 28: ee402ba5 vmla.f64 d18, d16, d21 + 2c: ee401ba6 vmla.f64 d17, d16, d22 + 30: ee600b20 vmul.f64 d16, d0, d16 + 34: ee645ba0 vmul.f64 d21, d20, d16 + 38: ee431ba4 vmla.f64 d17, d19, d20 + 3c: ee020ba0 vmla.f64 d0, d18, d16 + 40: 1eff0b00 vmovne.f64 d16, #240 ; 0xbf800000 -1.0 + 44: ee010ba5 vmla.f64 d0, d17, d21 + 48: 1e800b80 vdivne.f64 d0, d16, d0 + 4c: eeb70bc0 vcvt.f32.f64 s0, d0 + 50: e12fff1e bx lr + 54: e320f000 nop {0} + 58: bf971bcd .word 0xbf971bcd + 5c: 3f8362b9 .word 0x3f8362b9 + 60: fcecf44e .word 0xfcecf44e + 64: 3f685dad .word 0x3f685dad + 68: 908c33ce .word 0x908c33ce + 6c: 3f991df3 .word 0x3f991df3 + 70: 38999f72 .word 0x38999f72 + 74: 3fc112fd .word 0x3fc112fd + 78: 1d865afe .word 0x1d865afe + 7c: 3fab54c9 .word 0x3fab54c9 + 80: 3418c99f .word 0x3418c99f + 84: 3fd5554d .word 0x3fd5554d + +Disassembly of section .text.acosf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 8: e35305fe cmp r3, #1065353216 ; 0x3f800000 + c: 3a000004 bcc 24 + 10: 1a00002c bne c8 + 14: e3520000 cmp r2, #0 + 18: ba000040 blt 120 + 1c: ed9f0a57 vldr s0, [pc, #348] ; 180 + 20: e12fff1e bx lr + 24: e353043f cmp r3, #1056964608 ; 0x3f000000 + 28: 2a000005 bcs 44 + 2c: e35305ca cmp r3, #847249408 ; 0x32800000 + 30: 8a000028 bhi d8 + 34: eddf7a52 vldr s15, [pc, #328] ; 184 + 38: ed9f0a52 vldr s0, [pc, #328] ; 188 + 3c: ee300a27 vadd.f32 s0, s0, s15 + 40: e12fff1e bx lr + 44: e92d4010 push {r4, lr} + 48: e3520000 cmp r2, #0 + 4c: eef67a00 vmov.f32 s15, #96 ; 0x3f000000 0.5 + 50: ed2d8b02 vpush {d8} + 54: eef78a00 vmov.f32 s17, #112 ; 0x3f800000 1.0 + 58: ba000034 blt 130 + 5c: ee380ac0 vsub.f32 s0, s17, s0 + 60: ee208a27 vmul.f32 s16, s0, s15 + 64: eeb00a48 vmov.f32 s0, s16 + 68: ebfffffe bl 0 + 68: R_ARM_CALL sqrtf + 6c: ed9f7a46 vldr s14, [pc, #280] ; 18c + 70: ed9f6a46 vldr s12, [pc, #280] ; 190 + 74: ee103a10 vmov r3, s0 + 78: eddf6a45 vldr s13, [pc, #276] ; 194 + 7c: eeb05a48 vmov.f32 s10, s16 + 80: eddf7a44 vldr s15, [pc, #272] ; 198 + 84: ee186a07 vnmls.f32 s12, s16, s14 + 88: eeb07a40 vmov.f32 s14, s0 + 8c: ee488a26 vmla.f32 s17, s16, s13 + 90: e7cb301f bfc r3, #0, #12 + 94: ee063a90 vmov s13, r3 + 98: ee065ae6 vmls.f32 s10, s13, s13 + 9c: ee705a26 vadd.f32 s11, s0, s13 + a0: ee467a08 vmla.f32 s15, s12, s16 + a4: ee850a25 vdiv.f32 s0, s10, s11 + a8: ee677a88 vmul.f32 s15, s15, s16 + ac: ee876aa8 vdiv.f32 s12, s15, s17 + b0: eef07a40 vmov.f32 s15, s0 + b4: ee467a07 vmla.f32 s15, s12, s14 + b8: ee370aa6 vadd.f32 s0, s15, s13 + bc: ee300a00 vadd.f32 s0, s0, s0 + c0: ecbd8b02 vpop {d8} + c4: e8bd8010 pop {r4, pc} + c8: ee707a40 vsub.f32 s15, s0, s0 + cc: ed9f7a2b vldr s14, [pc, #172] ; 180 + d0: ee870a27 vdiv.f32 s0, s14, s15 + d4: e12fff1e bx lr + d8: ee606a00 vmul.f32 s13, s0, s0 + dc: ed9f4a2a vldr s8, [pc, #168] ; 18c + e0: ed9f5a2a vldr s10, [pc, #168] ; 190 + e4: eef75a00 vmov.f32 s11, #112 ; 0x3f800000 1.0 + e8: ed9f7a2a vldr s14, [pc, #168] ; 198 + ec: eddf4a28 vldr s9, [pc, #160] ; 194 + f0: ee165a84 vnmls.f32 s10, s13, s8 + f4: ed9f6a28 vldr s12, [pc, #160] ; 19c + f8: eddf7a22 vldr s15, [pc, #136] ; 188 + fc: ee465aa4 vmla.f32 s11, s13, s9 + 100: ee057a26 vmla.f32 s14, s10, s13 + 104: ee277a26 vmul.f32 s14, s14, s13 + 108: eec76a25 vdiv.f32 s13, s14, s11 + 10c: eeb07a46 vmov.f32 s14, s12 + 110: ee067ac0 vmls.f32 s14, s13, s0 + 114: ee300a47 vsub.f32 s0, s0, s14 + 118: ee370ac0 vsub.f32 s0, s15, s0 + 11c: e12fff1e bx lr + 120: eddf7a17 vldr s15, [pc, #92] ; 184 + 124: ed9f0a1d vldr s0, [pc, #116] ; 1a0 + 128: ee300a27 vadd.f32 s0, s0, s15 + 12c: e12fff1e bx lr + 130: ee300a28 vadd.f32 s0, s0, s17 + 134: ee208a27 vmul.f32 s16, s0, s15 + 138: eeb00a48 vmov.f32 s0, s16 + 13c: ebfffffe bl 0 + 13c: R_ARM_CALL sqrtf + 140: ed9f5a11 vldr s10, [pc, #68] ; 18c + 144: ed9f6a11 vldr s12, [pc, #68] ; 190 + 148: eddf6a12 vldr s13, [pc, #72] ; 198 + 14c: eddf5a10 vldr s11, [pc, #64] ; 194 + 150: ee186a05 vnmls.f32 s12, s16, s10 + 154: ed9f7a10 vldr s14, [pc, #64] ; 19c + 158: eddf7a0a vldr s15, [pc, #40] ; 188 + 15c: ee488a25 vmla.f32 s17, s16, s11 + 160: ee466a08 vmla.f32 s13, s12, s16 + 164: ee666a88 vmul.f32 s13, s13, s16 + 168: ee866aa8 vdiv.f32 s12, s13, s17 + 16c: ee167a00 vnmls.f32 s14, s12, s0 + 170: ee377a00 vadd.f32 s14, s14, s0 + 174: ee370ac7 vsub.f32 s0, s15, s14 + 178: ee300a00 vadd.f32 s0, s0, s0 + 17c: eaffffcf b c0 + 180: 00000000 .word 0x00000000 + 184: 03800000 .word 0x03800000 + 188: 3fc90fda .word 0x3fc90fda + 18c: bc0dd36b .word 0xbc0dd36b + 190: 3d2f13ba .word 0x3d2f13ba + 194: bf34e5ae .word 0xbf34e5ae + 198: 3e2aaa75 .word 0x3e2aaa75 + 19c: 33a22168 .word 0x33a22168 + 1a0: 40490fda .word 0x40490fda + +Disassembly of section .text.asinf: + +00000000 : + 0: e92d4010 push {r4, lr} + 4: ee104a10 vmov r4, s0 + 8: eef07a40 vmov.f32 s15, s0 + c: ed2d8b02 vpush {d8} + 10: e3c43102 bic r3, r4, #-2147483648 ; 0x80000000 + 14: e35305fe cmp r3, #1065353216 ; 0x3f800000 + 18: 3a000009 bcc 44 + 1c: 1e777ae7 vsubne.f32 s15, s15, s15 + 20: 1d9f7a3a vldrne s14, [pc, #232] ; 110 + 24: 0eb70ac0 vcvteq.f64.f32 d0, s0 + 28: 0ddf0b34 vldreq d16, [pc, #208] ; 100 + 2c: 0ddf1b35 vldreq d17, [pc, #212] ; 108 + 30: 1e870a27 vdivne.f32 s0, s14, s15 + 34: 0e400b21 vmlaeq.f64 d16, d0, d17 + 38: 0eb70be0 vcvteq.f32.f64 s0, d16 + 3c: ecbd8b02 vpop {d8} + 40: e8bd8010 pop {r4, pc} + 44: e353043f cmp r3, #1056964608 ; 0x3f000000 + 48: 2a000011 bcs 94 + 4c: e2433502 sub r3, r3, #8388608 ; 0x800000 + 50: e3530439 cmp r3, #956301312 ; 0x39000000 + 54: 3afffff8 bcc 3c + 58: ee676aa7 vmul.f32 s13, s15, s15 + 5c: eddf4a2c vldr s9, [pc, #176] ; 114 + 60: eddf5a2c vldr s11, [pc, #176] ; 118 + 64: eeb76a00 vmov.f32 s12, #112 ; 0x3f800000 1.0 + 68: ed9f7a2b vldr s14, [pc, #172] ; 11c + 6c: ed9f5a2b vldr s10, [pc, #172] ; 120 + 70: ee565aa4 vnmls.f32 s11, s13, s9 + 74: ecbd8b02 vpop {d8} + 78: ee066a85 vmla.f32 s12, s13, s10 + 7c: ee057aa6 vmla.f32 s14, s11, s13 + 80: ee277a26 vmul.f32 s14, s14, s13 + 84: eec76a06 vdiv.f32 s13, s14, s12 + 88: ee467aa7 vmla.f32 s15, s13, s15 + 8c: eeb00a67 vmov.f32 s0, s15 + 90: e8bd8010 pop {r4, pc} + 94: eef78a00 vmov.f32 s17, #112 ; 0x3f800000 1.0 + 98: ebfffffe bl 0 + 98: R_ARM_CALL fabsf + 9c: eef67a00 vmov.f32 s15, #96 ; 0x3f000000 0.5 + a0: ee388ac0 vsub.f32 s16, s17, s0 + a4: ee288a27 vmul.f32 s16, s16, s15 + a8: eeb70ac8 vcvt.f64.f32 d0, s16 + ac: ebfffffe bl 0 + ac: R_ARM_CALL sqrt + b0: ed9f6a17 vldr s12, [pc, #92] ; 114 + b4: ed9f7a17 vldr s14, [pc, #92] ; 118 + b8: e3540000 cmp r4, #0 + bc: eddf7a16 vldr s15, [pc, #88] ; 11c + c0: eddf6a16 vldr s13, [pc, #88] ; 120 + c4: ee187a06 vnmls.f32 s14, s16, s12 + c8: eddf0b0e vldr d16, [pc, #56] ; 108 + cc: ee488a26 vmla.f32 s17, s16, s13 + d0: ee477a08 vmla.f32 s15, s14, s16 + d4: ee677a88 vmul.f32 s15, s15, s16 + d8: ee877aa8 vdiv.f32 s14, s15, s17 + dc: ecbd8b02 vpop {d8} + e0: eeb77ac7 vcvt.f64.f32 d7, s14 + e4: ee070b00 vmla.f64 d0, d7, d0 + e8: ee300b00 vadd.f64 d0, d0, d0 + ec: ee300bc0 vsub.f64 d0, d16, d0 + f0: eeb70bc0 vcvt.f32.f64 s0, d0 + f4: beb10a40 vneglt.f32 s0, s0 + f8: e8bd8010 pop {r4, pc} + fc: e320f000 nop {0} + 100: 00000000 .word 0x00000000 + 104: 38700000 .word 0x38700000 + 108: 54442d18 .word 0x54442d18 + 10c: 3ff921fb .word 0x3ff921fb + 110: 00000000 .word 0x00000000 + 114: bc0dd36b .word 0xbc0dd36b + 118: 3d2f13ba .word 0x3d2f13ba + 11c: 3e2aaa75 .word 0x3e2aaa75 + 120: bf34e5ae .word 0xbf34e5ae + +Disassembly of section .text.atan2f: + +00000000 : + 0: ee103a90 vmov r3, s1 + 4: e3a02000 mov r2, #0 + 8: e3472f80 movt r2, #32640 ; 0x7f80 + c: eef07a40 vmov.f32 s15, s0 + 10: e3c31102 bic r1, r3, #-2147483648 ; 0x80000000 + 14: e1510002 cmp r1, r2 + 18: 8a000024 bhi b0 + 1c: ee10ca10 vmov ip, s0 + 20: e3cc0102 bic r0, ip, #-2147483648 ; 0x80000000 + 24: e1500002 cmp r0, r2 + 28: 8a000020 bhi b0 + 2c: e35305fe cmp r3, #1065353216 ; 0x3f800000 + 30: 0a00002d beq ec + 34: e92d4010 push {r4, lr} + 38: e1a04f23 lsr r4, r3, #30 + 3c: e2044002 and r4, r4, #2 + 40: e3500000 cmp r0, #0 + 44: e1844fac orr r4, r4, ip, lsr #31 + 48: 0a00001a beq b8 + 4c: e3510000 cmp r1, #0 + 50: 0a00001e beq d0 + 54: e1510002 cmp r1, r2 + 58: 0a000024 beq f0 + 5c: e0402002 sub r2, r0, r2 + 60: e281340d add r3, r1, #218103808 ; 0xd000000 + 64: e16f2f12 clz r2, r2 + 68: e1a022a2 lsr r2, r2, #5 + 6c: e1500003 cmp r0, r3 + 70: 83822001 orrhi r2, r2, #1 + 74: e3520000 cmp r2, #0 + 78: 1a000014 bne d0 + 7c: e3140002 tst r4, #2 + 80: 0a000038 beq 168 + 84: e280040d add r0, r0, #218103808 ; 0xd000000 + 88: e1510000 cmp r1, r0 + 8c: 9a000021 bls 118 + 90: ed9f0a49 vldr s0, [pc, #292] ; 1bc + 94: e3540002 cmp r4, #2 + 98: 0a000023 beq 12c + 9c: ed9f7a47 vldr s14, [pc, #284] ; 1c0 + a0: eddf7a47 vldr s15, [pc, #284] ; 1c4 + a4: ee300a07 vadd.f32 s0, s0, s14 + a8: ee300a67 vsub.f32 s0, s0, s15 + ac: e8bd8010 pop {r4, pc} + b0: ee300aa7 vadd.f32 s0, s1, s15 + b4: e12fff1e bx lr + b8: e3540002 cmp r4, #2 + bc: 0a000008 beq e4 + c0: ed9f7a40 vldr s14, [pc, #256] ; 1c8 + c4: e3540003 cmp r4, #3 + c8: 0eb00a47 vmoveq.f32 s0, s14 + cc: e8bd8010 pop {r4, pc} + d0: eddf7a3d vldr s15, [pc, #244] ; 1cc + d4: e3140001 tst r4, #1 + d8: ed9f0a3c vldr s0, [pc, #240] ; 1d0 + dc: 0eb00a67 vmoveq.f32 s0, s15 + e0: e8bd8010 pop {r4, pc} + e4: ed9f0a36 vldr s0, [pc, #216] ; 1c4 + e8: e8bd8010 pop {r4, pc} + ec: eafffffe b 0 + ec: R_ARM_JUMP24 atanf + f0: e1500001 cmp r0, r1 + f4: 0a000011 beq 140 + f8: e2444001 sub r4, r4, #1 + fc: e3540002 cmp r4, #2 + 100: 8a00001f bhi 184 + 104: e3003000 movw r3, #0 + 104: R_ARM_MOVW_ABS_NC CSWTCH.7 + 108: e3403000 movt r3, #0 + 108: R_ARM_MOVT_ABS CSWTCH.7 + 10c: e0833104 add r3, r3, r4, lsl #2 + 110: ed930a00 vldr s0, [r3] + 114: e8bd8010 pop {r4, pc} + 118: ee870aa0 vdiv.f32 s0, s15, s1 + 11c: ebfffffe bl 0 + 11c: R_ARM_CALL fabsf + 120: ebfffffe bl 0 + 120: R_ARM_CALL atanf + 124: e3540002 cmp r4, #2 + 128: 1affffdb bne 9c + 12c: ed9f7a23 vldr s14, [pc, #140] ; 1c0 + 130: eddf7a23 vldr s15, [pc, #140] ; 1c4 + 134: ee300a07 vadd.f32 s0, s0, s14 + 138: ee370ac0 vsub.f32 s0, s15, s0 + 13c: e8bd8010 pop {r4, pc} + 140: e3540002 cmp r4, #2 + 144: 0a000016 beq 1a4 + 148: e3540003 cmp r4, #3 + 14c: 0a00000e beq 18c + 150: eddf7a1f vldr s15, [pc, #124] ; 1d4 + 154: e3540001 cmp r4, #1 + 158: ed9f7a1e vldr s14, [pc, #120] ; 1d8 + 15c: 1eb00a47 vmovne.f32 s0, s14 + 160: 0eb00a67 vmoveq.f32 s0, s15 + 164: e8bd8010 pop {r4, pc} + 168: ee870aa0 vdiv.f32 s0, s15, s1 + 16c: ebfffffe bl 0 + 16c: R_ARM_CALL fabsf + 170: ebfffffe bl 0 + 170: R_ARM_CALL atanf + 174: e3540001 cmp r4, #1 + 178: 18bd8010 popne {r4, pc} + 17c: eeb10a40 vneg.f32 s0, s0 + 180: e8bd8010 pop {r4, pc} + 184: ed9f0a0c vldr s0, [pc, #48] ; 1bc + 188: e8bd8010 pop {r4, pc} + 18c: eddf7a0c vldr s15, [pc, #48] ; 1c4 + 190: eef86a08 vmov.f32 s13, #136 ; 0xc0400000 -3.0 + 194: eeb57a00 vmov.f32 s14, #80 ; 0x3e800000 0.250 + 198: ee677aa6 vmul.f32 s15, s15, s13 + 19c: ee270a87 vmul.f32 s0, s15, s14 + 1a0: e8bd8010 pop {r4, pc} + 1a4: eddf7a06 vldr s15, [pc, #24] ; 1c4 + 1a8: eef06a08 vmov.f32 s13, #8 ; 0x40400000 3.0 + 1ac: eeb57a00 vmov.f32 s14, #80 ; 0x3e800000 0.250 + 1b0: ee677aa6 vmul.f32 s15, s15, s13 + 1b4: ee270a87 vmul.f32 s0, s15, s14 + 1b8: e8bd8010 pop {r4, pc} + 1bc: 00000000 .word 0x00000000 + 1c0: 33bbbd2e .word 0x33bbbd2e + 1c4: 40490fdb .word 0x40490fdb + 1c8: c0490fdb .word 0xc0490fdb + 1cc: 3fc90fdb .word 0x3fc90fdb + 1d0: bfc90fdb .word 0xbfc90fdb + 1d4: bf490fdb .word 0xbf490fdb + 1d8: 3f490fdb .word 0x3f490fdb + +Disassembly of section .text.atanf: + +00000000 : + 0: ee103a10 vmov r3, s0 + 4: e92d4030 push {r4, r5, lr} + 8: e30f2fff movw r2, #65535 ; 0xffff + c: e3442c7f movt r2, #19583 ; 0x4c7f + 10: eef07a40 vmov.f32 s15, s0 + 14: e24dd00c sub sp, sp, #12 + 18: e3c34102 bic r4, r3, #-2147483648 ; 0x80000000 + 1c: e1a05fa3 lsr r5, r3, #31 + 20: e1540002 cmp r4, r2 + 24: 9a000006 bls 44 + 28: e3a03000 mov r3, #0 + 2c: e3473f80 movt r3, #32640 ; 0x7f80 + 30: e1540003 cmp r4, r3 + 34: 9a000016 bls 94 + 38: eeb00a67 vmov.f32 s0, s15 + 3c: e28dd00c add sp, sp, #12 + 40: e8bd8030 pop {r4, r5, pc} + 44: e30f2fff movw r2, #65535 ; 0xffff + 48: e3432edf movt r2, #16095 ; 0x3edf + 4c: e1540002 cmp r4, r2 + 50: 8a000017 bhi b4 + 54: e35405e6 cmp r4, #964689920 ; 0x39800000 + 58: 3a000027 bcc fc + 5c: ee206a00 vmul.f32 s12, s0, s0 + 60: ed9f4a55 vldr s8, [pc, #340] ; 1bc + 64: ed9f5a55 vldr s10, [pc, #340] ; 1c0 + 68: eddf4a55 vldr s9, [pc, #340] ; 1c4 + 6c: ed9f7a55 vldr s14, [pc, #340] ; 1c8 + 70: ee666a06 vmul.f32 s13, s12, s12 + 74: eddf5a54 vldr s11, [pc, #336] ; 1cc + 78: ee065a84 vmla.f32 s10, s13, s8 + 7c: ee167aa4 vnmls.f32 s14, s13, s9 + 80: ee455a26 vmla.f32 s11, s10, s13 + 84: ee277a26 vmul.f32 s14, s14, s13 + 88: ee057a86 vmla.f32 s14, s11, s12 + 8c: ee477a40 vmls.f32 s15, s14, s0 + 90: eaffffe8 b 38 + 94: eddf7a4d vldr s15, [pc, #308] ; 1d0 + 98: e3550000 cmp r5, #0 + 9c: ed9f7a4c vldr s14, [pc, #304] ; 1d4 + a0: ee370a87 vadd.f32 s0, s15, s14 + a4: 0affffe4 beq 3c + a8: eeb10a40 vneg.f32 s0, s0 + ac: e28dd00c add sp, sp, #12 + b0: e8bd8030 pop {r4, r5, pc} + b4: ebfffffe bl 0 + b4: R_ARM_CALL fabsf + b8: e30f3fff movw r3, #65535 ; 0xffff + bc: e3433f97 movt r3, #16279 ; 0x3f97 + c0: e1540003 cmp r4, r3 + c4: e30f3fff movw r3, #65535 ; 0xffff + c8: 8a000012 bhi 118 + cc: e3433f2f movt r3, #16175 ; 0x3f2f + d0: e1540003 cmp r4, r3 + d4: 8a000031 bhi 1a0 + d8: ee307a00 vadd.f32 s14, s0, s0 + dc: eef05a00 vmov.f32 s11, #0 ; 0x40000000 2.0 + e0: eeb76a00 vmov.f32 s12, #112 ; 0x3f800000 1.0 + e4: eddf6a3b vldr s13, [pc, #236] ; 1d8 + e8: ee300a25 vadd.f32 s0, s0, s11 + ec: eddf7a3a vldr s15, [pc, #232] ; 1dc + f0: ee377a46 vsub.f32 s14, s14, s12 + f4: eec75a00 vdiv.f32 s11, s14, s0 + f8: ea00000d b 134 + fc: e3a02000 mov r2, #0 + 100: e3472f80 movt r2, #32640 ; 0x7f80 + 104: e0022003 and r2, r2, r3 + 108: e3520000 cmp r2, #0 + 10c: 0e207a00 vmuleq.f32 s14, s0, s0 + 110: 0d8d7a01 vstreq s14, [sp, #4] + 114: eaffffc7 b 38 + 118: e344301b movt r3, #16411 ; 0x401b + 11c: e1540003 cmp r4, r3 + 120: 9a000016 bls 180 + 124: eebf7a00 vmov.f32 s14, #240 ; 0xbf800000 -1.0 + 128: eddf6a2c vldr s13, [pc, #176] ; 1e0 + 12c: eddf7a27 vldr s15, [pc, #156] ; 1d0 + 130: eec75a00 vdiv.f32 s11, s14, s0 + 134: ee255aa5 vmul.f32 s10, s11, s11 + 138: ed9f3a1f vldr s6, [pc, #124] ; 1bc + 13c: ed9f4a1f vldr s8, [pc, #124] ; 1c0 + 140: e3550000 cmp r5, #0 + 144: eddf3a1e vldr s7, [pc, #120] ; 1c4 + 148: ed9f7a1e vldr s14, [pc, #120] ; 1c8 + 14c: ee256a05 vmul.f32 s12, s10, s10 + 150: eddf4a1d vldr s9, [pc, #116] ; 1cc + 154: ee064a03 vmla.f32 s8, s12, s6 + 158: ee167a23 vnmls.f32 s14, s12, s7 + 15c: ee444a06 vmla.f32 s9, s8, s12 + 160: ee277a06 vmul.f32 s14, s14, s12 + 164: ee047a85 vmla.f32 s14, s9, s10 + 168: ee576a25 vnmls.f32 s13, s14, s11 + 16c: ee367ae5 vsub.f32 s14, s13, s11 + 170: ee370ac7 vsub.f32 s0, s15, s14 + 174: 0affffb0 beq 3c + 178: eeb10a40 vneg.f32 s0, s0 + 17c: eaffffca b ac + 180: eeb76a08 vmov.f32 s12, #120 ; 0x3fc00000 1.5 + 184: eeb77a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 + 188: eddf6a15 vldr s13, [pc, #84] ; 1e4 + 18c: ee007a06 vmla.f32 s14, s0, s12 + 190: ee300a46 vsub.f32 s0, s0, s12 + 194: eddf7a13 vldr s15, [pc, #76] ; 1e8 + 198: eec05a07 vdiv.f32 s11, s0, s14 + 19c: eaffffe4 b 134 + 1a0: eeb77a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 + 1a4: eddf6a10 vldr s13, [pc, #64] ; 1ec + 1a8: eddf7a10 vldr s15, [pc, #64] ; 1f0 + 1ac: ee306a47 vsub.f32 s12, s0, s14 + 1b0: ee300a07 vadd.f32 s0, s0, s14 + 1b4: eec65a00 vdiv.f32 s11, s12, s0 + 1b8: eaffffdd b 134 + 1bc: 3d7cac25 .word 0x3d7cac25 + 1c0: 3e11f50d .word 0x3e11f50d + 1c4: bdda1247 .word 0xbdda1247 + 1c8: 3e4cca98 .word 0x3e4cca98 + 1cc: 3eaaaaa9 .word 0x3eaaaaa9 + 1d0: 3fc90fda .word 0x3fc90fda + 1d4: 03800000 .word 0x03800000 + 1d8: 31ac3769 .word 0x31ac3769 + 1dc: 3eed6338 .word 0x3eed6338 + 1e0: 33a22168 .word 0x33a22168 + 1e4: 33140fb4 .word 0x33140fb4 + 1e8: 3f7b985e .word 0x3f7b985e + 1ec: 33222168 .word 0x33222168 + 1f0: 3f490fda .word 0x3f490fda + +Disassembly of section .text.cosf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e3001fda movw r1, #4058 ; 0xfda + c: e3431f49 movt r1, #16201 ; 0x3f49 + 10: eef07a40 vmov.f32 s15, s0 + 14: e24dd00c sub sp, sp, #12 + 18: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 1c: e1530001 cmp r3, r1 + 20: 8a000007 bhi 44 + 24: e35305e6 cmp r3, #964689920 ; 0x39800000 + 28: 2a000026 bcs c8 + 2c: ed9f7a55 vldr s14, [pc, #340] ; 188 + 30: eeb70a00 vmov.f32 s0, #112 ; 0x3f800000 1.0 + 34: ee777a87 vadd.f32 s15, s15, s14 + 38: edcd7a00 vstr s15, [sp] + 3c: e28dd00c add sp, sp, #12 + 40: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 44: e30513d1 movw r1, #21457 ; 0x53d1 + 48: e344107b movt r1, #16507 ; 0x407b + 4c: e1a02fa2 lsr r2, r2, #31 + 50: e1530001 cmp r3, r1 + 54: 8a00000b bhi 88 + 58: e30c1be3 movw r1, #52195 ; 0xcbe3 + 5c: e3441016 movt r1, #16406 ; 0x4016 + 60: eeb70ac0 vcvt.f64.f32 d0, s0 + 64: e1530001 cmp r3, r1 + 68: 8a00002b bhi 11c + 6c: eddf0b3d vldr d16, [pc, #244] ; 168 + 70: e3520000 cmp r2, #0 + 74: 1e300b20 vaddne.f64 d0, d0, d16 + 78: 0e300bc0 vsubeq.f64 d0, d16, d0 + 7c: e28dd00c add sp, sp, #12 + 80: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 84: eafffffe b 0 + 84: R_ARM_JUMP24 __sindf + 88: e30311d5 movw r1, #12757 ; 0x31d5 + 8c: e34410e2 movt r1, #16610 ; 0x40e2 + 90: e1530001 cmp r3, r1 + 94: 8a00000f bhi d8 + 98: e30e1ddf movw r1, #60895 ; 0xeddf + 9c: e34410af movt r1, #16559 ; 0x40af + a0: e1530001 cmp r3, r1 + a4: 8a000027 bhi 148 + a8: e3520000 cmp r2, #0 + ac: 1eb10a40 vnegne.f32 s0, s0 + b0: 0eb70ae7 vcvteq.f64.f32 d0, s15 + b4: 1ddf0b2d vldrne d16, [pc, #180] ; 170 + b8: 0ddf0b2c vldreq d16, [pc, #176] ; 170 + bc: 1eb70ac0 vcvtne.f64.f32 d0, s0 + c0: ee300b60 vsub.f64 d0, d0, d16 + c4: eaffffec b 7c + c8: eeb70ac0 vcvt.f64.f32 d0, s0 + cc: e28dd00c add sp, sp, #12 + d0: e49de004 pop {lr} ; (ldr lr, [sp], #4) + d4: eafffffe b 0 + d4: R_ARM_JUMP24 __cosdf + d8: e30f2fff movw r2, #65535 ; 0xffff + dc: e3472f7f movt r2, #32639 ; 0x7f7f + e0: e1530002 cmp r3, r2 + e4: 8e300a40 vsubhi.f32 s0, s0, s0 + e8: 8affffd3 bhi 3c + ec: e1a0000d mov r0, sp + f0: ebfffffe bl 0 + f0: R_ARM_CALL __rem_pio2f + f4: e2000003 and r0, r0, #3 + f8: ed9d0b00 vldr d0, [sp] + fc: e3500001 cmp r0, #1 + 100: 0a00000d beq 13c + 104: e3500002 cmp r0, #2 + 108: 0a000007 beq 12c + 10c: e3500000 cmp r0, #0 + 110: 1a000012 bne 160 + 114: ebfffffe bl 0 + 114: R_ARM_CALL __cosdf + 118: eaffffc7 b 3c + 11c: eddf0b15 vldr d16, [pc, #84] ; 178 + 120: e3520000 cmp r2, #0 + 124: 1e300b20 vaddne.f64 d0, d0, d16 + 128: 0e300b60 vsubeq.f64 d0, d0, d16 + 12c: ebfffffe bl 0 + 12c: R_ARM_CALL __cosdf + 130: eeb10a40 vneg.f32 s0, s0 + 134: e28dd00c add sp, sp, #12 + 138: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 13c: eeb10b40 vneg.f64 d0, d0 + 140: ebfffffe bl 0 + 140: R_ARM_CALL __sindf + 144: eaffffbc b 3c + 148: eeb70ac0 vcvt.f64.f32 d0, s0 + 14c: eddf0b0b vldr d16, [pc, #44] ; 180 + 150: e3520000 cmp r2, #0 + 154: 1e300b20 vaddne.f64 d0, d0, d16 + 158: 0e300b60 vsubeq.f64 d0, d0, d16 + 15c: eaffffda b cc + 160: ebfffffe bl 0 + 160: R_ARM_CALL __sindf + 164: eaffffb4 b 3c + 168: 54442d18 .word 0x54442d18 + 16c: 3ff921fb .word 0x3ff921fb + 170: 7f3321d2 .word 0x7f3321d2 + 174: 4012d97c .word 0x4012d97c + 178: 54442d18 .word 0x54442d18 + 17c: 400921fb .word 0x400921fb + 180: 54442d18 .word 0x54442d18 + 184: 401921fb .word 0x401921fb + 188: 7b800000 .word 0x7b800000 + +Disassembly of section .text.expf: + +00000000 : + 0: ee103a10 vmov r3, s0 + 4: e300142a movw r1, #1066 ; 0x42a + 8: eef70ac0 vcvt.f64.f32 d16, s0 + c: e7ea2a53 ubfx r2, r3, #20, #11 + 10: e1520001 cmp r2, r1 + 14: 8a00001c bhi 8c + 18: e3003000 movw r3, #0 + 18: R_ARM_MOVW_ABS_NC __exp2f_data + 1c: e3403000 movt r3, #0 + 1c: R_ARM_MOVT_ABS __exp2f_data + 20: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + 24: e92d4010 push {r4, lr} + 28: e3a0c000 mov ip, #0 + 2c: edd35b4a vldr d21, [r3, #296] ; 0x128 + 30: edd31b48 vldr d17, [r3, #288] ; 0x120 + 34: edd34b4c vldr d20, [r3, #304] ; 0x130 + 38: ee600ba5 vmul.f64 d16, d16, d21 + 3c: edd32b4e vldr d18, [r3, #312] ; 0x138 + 40: edd33b50 vldr d19, [r3, #320] ; 0x140 + 44: ee317ba0 vadd.f64 d7, d17, d16 + 48: ee771b61 vsub.f64 d17, d7, d17 + 4c: ee172a10 vmov r2, s14 + 50: ee700be1 vsub.f64 d16, d16, d17 + 54: e202e01f and lr, r2, #31 + 58: e083418e add r4, r3, lr, lsl #3 + 5c: e793318e ldr r3, [r3, lr, lsl #3] + 60: ee402ba4 vmla.f64 d18, d16, d20 + 64: ee000ba3 vmla.f64 d0, d16, d19 + 68: ee600ba0 vmul.f64 d16, d16, d16 + 6c: e09c0003 adds r0, ip, r3 + 70: e5943004 ldr r3, [r4, #4] + 74: e0831782 add r1, r3, r2, lsl #15 + 78: ee020ba0 vmla.f64 d0, d18, d16 + 7c: ec410b30 vmov d16, r0, r1 + 80: ee200b20 vmul.f64 d0, d0, d16 + 84: eeb70bc0 vcvt.f32.f64 s0, d0 + 88: e8bd8010 pop {r4, pc} + 8c: e3730502 cmn r3, #8388608 ; 0x800000 + 90: 0a000010 beq d8 + 94: e30037f7 movw r3, #2039 ; 0x7f7 + 98: e1520003 cmp r2, r3 + 9c: 8a00000b bhi d0 + a0: eddf7a0e vldr s15, [pc, #56] ; e0 + a4: eeb40ae7 vcmpe.f32 s0, s15 + a8: eef1fa10 vmrs APSR_nzcv, fpscr + ac: ca000005 bgt c8 + b0: eddf7a0b vldr s15, [pc, #44] ; e4 + b4: eeb40ae7 vcmpe.f32 s0, s15 + b8: eef1fa10 vmrs APSR_nzcv, fpscr + bc: 5affffd5 bpl 18 + c0: e3a00000 mov r0, #0 + c4: eafffffe b 0 + c4: R_ARM_JUMP24 __math_uflowf + c8: e3a00000 mov r0, #0 + cc: eafffffe b 0 + cc: R_ARM_JUMP24 __math_oflowf + d0: ee300a00 vadd.f32 s0, s0, s0 + d4: e12fff1e bx lr + d8: ed9f0a02 vldr s0, [pc, #8] ; e8 + dc: e12fff1e bx lr + e0: 42b17217 .word 0x42b17217 + e4: c2cff1b4 .word 0xc2cff1b4 + e8: 00000000 .word 0x00000000 + +Disassembly of section .text.fabsf: + +00000000 : + 0: eeb00ac0 vabs.f32 s0, s0 + 4: e12fff1e bx lr + +Disassembly of section .text.floor: + +00000000 : + 0: eeb50b40 vcmp.f64 d0, #0.0 + 4: ee102a90 vmov r2, s1 + 8: e3000432 movw r0, #1074 ; 0x432 + c: eef1fa10 vmrs APSR_nzcv, fpscr + 10: e7ea1a52 ubfx r1, r2, #20, #11 + 14: 03a03001 moveq r3, #1 + 18: 13a03000 movne r3, #0 + 1c: e1510000 cmp r1, r0 + 20: c3833001 orrgt r3, r3, #1 + 24: e3530000 cmp r3, #0 + 28: 112fff1e bxne lr + 2c: e24dd008 sub sp, sp, #8 + 30: eddf1b18 vldr d17, [pc, #96] ; 98 + 34: e3520000 cmp r2, #0 + 38: e30033fe movw r3, #1022 ; 0x3fe + 3c: ba00000d blt 78 + 40: ee700b21 vadd.f64 d16, d0, d17 + 44: e1510003 cmp r1, r3 + 48: ee700be1 vsub.f64 d16, d16, d17 + 4c: ee700bc0 vsub.f64 d16, d16, d0 + 50: dd9f0b12 vldrle d0, [pc, #72] ; a0 + 54: ddcd0b00 vstrle d16, [sp] + 58: da000004 ble 70 + 5c: eef50bc0 vcmpe.f64 d16, #0.0 + 60: ee300b20 vadd.f64 d0, d0, d16 + 64: eef1fa10 vmrs APSR_nzcv, fpscr + 68: cef70b00 vmovgt.f64 d16, #112 ; 0x3f800000 1.0 + 6c: ce300b60 vsubgt.f64 d0, d0, d16 + 70: e28dd008 add sp, sp, #8 + 74: e12fff1e bx lr + 78: ee700b61 vsub.f64 d16, d0, d17 + 7c: e1510003 cmp r1, r3 + 80: ee700ba1 vadd.f64 d16, d16, d17 + 84: ee700bc0 vsub.f64 d16, d16, d0 + 88: debf0b00 vmovle.f64 d0, #240 ; 0xbf800000 -1.0 + 8c: ddcd0b00 vstrle d16, [sp] + 90: cafffff1 bgt 5c + 94: eafffff5 b 70 + 98: 00000000 .word 0x00000000 + 9c: 43300000 .word 0x43300000 + ... + +Disassembly of section .text.floorf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e7e73bd2 ubfx r3, r2, #23, #8 + 8: e243307f sub r3, r3, #127 ; 0x7f + c: e3530016 cmp r3, #22 + 10: c12fff1e bxgt lr + 14: e24dd008 sub sp, sp, #8 + 18: e3530000 cmp r3, #0 + 1c: ba00000d blt 58 + 20: e30f1fff movw r1, #65535 ; 0xffff + 24: e340107f movt r1, #127 ; 0x7f + 28: e1a01351 asr r1, r1, r3 + 2c: e1120001 tst r2, r1 + 30: 0a000006 beq 50 + 34: eddf7a13 vldr s15, [pc, #76] ; 88 + 38: e3520000 cmp r2, #0 + 3c: b0822001 addlt r2, r2, r1 + 40: e1c23001 bic r3, r2, r1 + 44: ee300a27 vadd.f32 s0, s0, s15 + 48: ed8d0a00 vstr s0, [sp] + 4c: ee003a10 vmov s0, r3 + 50: e28dd008 add sp, sp, #8 + 54: e12fff1e bx lr + 58: eddf7a0a vldr s15, [pc, #40] ; 88 + 5c: e3520000 cmp r2, #0 + 60: ee300a27 vadd.f32 s0, s0, s15 + 64: ed8d0a01 vstr s0, [sp, #4] + 68: ad9f0a07 vldrge s0, [pc, #28] ; 8c + 6c: aafffff7 bge 50 + 70: eddf7a06 vldr s15, [pc, #24] ; 90 + 74: e1b02082 lsls r2, r2, #1 + 78: eebf0a00 vmov.f32 s0, #240 ; 0xbf800000 -1.0 + 7c: 0eb00a67 vmoveq.f32 s0, s15 + 80: e28dd008 add sp, sp, #8 + 84: e12fff1e bx lr + 88: 7b800000 .word 0x7b800000 + 8c: 00000000 .word 0x00000000 + 90: 80000000 .word 0x80000000 + +Disassembly of section .text.logf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e35205fe cmp r2, #1065353216 ; 0x3f800000 + 8: 0a000020 beq 90 + c: e2423502 sub r3, r2, #8388608 ; 0x800000 + 10: e353047f cmp r3, #2130706432 ; 0x7f000000 + 14: 2a00001f bcs 98 + 18: e2823103 add r3, r2, #-1073741824 ; 0xc0000000 + 1c: e3001000 movw r1, #0 + 1c: R_ARM_MOVW_ABS_NC __logf_data + 20: e3401000 movt r1, #0 + 20: R_ARM_MOVT_ABS __logf_data + 24: e28338cd add r3, r3, #13434880 ; 0xcd0000 + 28: eef72b00 vmov.f64 d18, #112 ; 0x3f800000 1.0 + 2c: e1a0cba3 lsr ip, r3, #23 + 30: e7e309d3 ubfx r0, r3, #19, #4 + 34: edd15b44 vldr d21, [r1, #272] ; 0x110 + 38: e1a03bc3 asr r3, r3, #23 + 3c: e1a0cb8c lsl ip, ip, #23 + 40: e0810200 add r0, r1, r0, lsl #4 + 44: e042200c sub r2, r2, ip + 48: ee072a90 vmov s15, r2 + 4c: edd13b46 vldr d19, [r1, #280] ; 0x118 + 50: eef71ae7 vcvt.f64.f32 d17, s15 + 54: edd06b00 vldr d22, [r0] + 58: ee073a90 vmov s15, r3 + 5c: edd17b40 vldr d23, [r1, #256] ; 0x100 + 60: edd14b42 vldr d20, [r1, #264] ; 0x108 + 64: eef80be7 vcvt.f64.s32 d16, s15 + 68: ed900b02 vldr d0, [r0, #8] + 6c: ee512ba6 vnmls.f64 d18, d17, d22 + 70: ee000ba7 vmla.f64 d0, d16, d23 + 74: ee621ba2 vmul.f64 d17, d18, d18 + 78: ee423ba5 vmla.f64 d19, d18, d21 + 7c: ee300b22 vadd.f64 d0, d0, d18 + 80: ee413ba4 vmla.f64 d19, d17, d20 + 84: ee030ba1 vmla.f64 d0, d19, d17 + 88: eeb70bc0 vcvt.f32.f64 s0, d0 + 8c: e12fff1e bx lr + 90: ed9f0a13 vldr s0, [pc, #76] ; e4 + 94: e12fff1e bx lr + 98: e1b03082 lsls r3, r2, #1 + 9c: 0a00000e beq dc + a0: e3a01000 mov r1, #0 + a4: e3471f80 movt r1, #32640 ; 0x7f80 + a8: e1520001 cmp r2, r1 + ac: 012fff1e bxeq lr + b0: e35304ff cmp r3, #-16777216 ; 0xff000000 + b4: 33a03000 movcc r3, #0 + b8: 23a03001 movcs r3, #1 + bc: e1933fa2 orrs r3, r3, r2, lsr #31 + c0: 1a000004 bne d8 + c4: ed9f7a07 vldr s14, [pc, #28] ; e8 + c8: ee607a07 vmul.f32 s15, s0, s14 + cc: ee173a90 vmov r3, s15 + d0: e243252e sub r2, r3, #192937984 ; 0xb800000 + d4: eaffffcf b 18 + d8: eafffffe b 0 + d8: R_ARM_JUMP24 __math_invalidf + dc: e3a00001 mov r0, #1 + e0: eafffffe b 0 + e0: R_ARM_JUMP24 __math_divzerof + e4: 00000000 .word 0x00000000 + e8: 4b000000 .word 0x4b000000 + +Disassembly of section .text.powf: + +00000000 : + 0: ee102a90 vmov r2, s1 + 4: ee10ca10 vmov ip, s0 + 8: e92d0030 push {r4, r5} + c: e3e00401 mvn r0, #16777216 ; 0x1000000 + 10: e24dd008 sub sp, sp, #8 + 14: e24c3502 sub r3, ip, #8388608 ; 0x800000 + 18: e1a01082 lsl r1, r2, #1 + 1c: e353047f cmp r3, #2130706432 ; 0x7f000000 + 20: e2413001 sub r3, r1, #1 + 24: 2a000046 bcs 144 + 28: e1530000 cmp r3, r0 + 2c: 33a00000 movcc r0, #0 + 30: 2a00005e bcs 1b0 + 34: e28c2103 add r2, ip, #-1073741824 ; 0xc0000000 + 38: e3001000 movw r1, #0 + 38: R_ARM_MOVW_ABS_NC __powf_log2_data + 3c: e3401000 movt r1, #0 + 3c: R_ARM_MOVT_ABS __powf_log2_data + 40: e28228cd add r2, r2, #13434880 ; 0xcd0000 + 44: eef70b00 vmov.f64 d16, #112 ; 0x3f800000 1.0 + 48: eef71ae0 vcvt.f64.f32 d17, s1 + 4c: e1a03ba2 lsr r3, r2, #23 + 50: e7e329d2 ubfx r2, r2, #19, #4 + 54: edd16b44 vldr d22, [r1, #272] ; 0x110 + 58: e1a03b83 lsl r3, r3, #23 + 5c: e0812202 add r2, r1, r2, lsl #4 + 60: e04cc003 sub ip, ip, r3 + 64: ee07ca90 vmov s15, ip + 68: edd13b46 vldr d19, [r1, #280] ; 0x118 + 6c: e1a03bc3 asr r3, r3, #23 + 70: eef77ae7 vcvt.f64.f32 d23, s15 + 74: edd29b00 vldr d25, [r2] + 78: ee073a10 vmov s14, r3 + 7c: edd28b02 vldr d24, [r2, #8] + 80: edd15b48 vldr d21, [r1, #288] ; 0x120 + 84: e30830bf movw r3, #32959 ; 0x80bf + 88: eeb87bc7 vcvt.f64.s32 d7, s14 + 8c: edd14b40 vldr d20, [r1, #256] ; 0x100 + 90: ee570ba9 vnmls.f64 d16, d23, d25 + 94: edd12b42 vldr d18, [r1, #264] ; 0x108 + 98: ee377b28 vadd.f64 d7, d7, d24 + 9c: ee403ba6 vmla.f64 d19, d16, d22 + a0: ee007ba5 vmla.f64 d7, d16, d21 + a4: ee402ba4 vmla.f64 d18, d16, d20 + a8: eef07b63 vmov.f64 d23, d19 + ac: ee603ba0 vmul.f64 d19, d16, d16 + b0: ee077ba3 vmla.f64 d7, d23, d19 + b4: ee630ba3 vmul.f64 d16, d19, d19 + b8: ee027ba0 vmla.f64 d7, d18, d16 + bc: ee277b21 vmul.f64 d7, d7, d17 + c0: ee172a90 vmov r2, s15 + c4: e7ef27d2 ubfx r2, r2, #15, #16 + c8: e1520003 cmp r2, r3 + cc: 2a00002c bcs 184 + d0: e3002000 movw r2, #0 + d0: R_ARM_MOVW_ABS_NC __exp2f_data + d4: e3402000 movt r2, #0 + d4: R_ARM_MOVT_ABS __exp2f_data + d8: eeb70b00 vmov.f64 d0, #112 ; 0x3f800000 1.0 + dc: e3a01000 mov r1, #0 + e0: edd20b40 vldr d16, [r2, #256] ; 0x100 + e4: edd23b42 vldr d19, [r2, #264] ; 0x108 + e8: edd21b44 vldr d17, [r2, #272] ; 0x110 + ec: ee376b20 vadd.f64 d6, d7, d16 + f0: edd22b46 vldr d18, [r2, #280] ; 0x118 + f4: ee760b60 vsub.f64 d16, d6, d16 + f8: ee163a10 vmov r3, s12 + fc: ee770b60 vsub.f64 d16, d7, d16 + 100: e0900003 adds r0, r0, r3 + 104: e203301f and r3, r3, #31 + 108: e082c183 add ip, r2, r3, lsl #3 + 10c: ee401ba3 vmla.f64 d17, d16, d19 + 110: ee000ba2 vmla.f64 d0, d16, d18 + 114: ee600ba0 vmul.f64 d16, d16, d16 + 118: e7923183 ldr r3, [r2, r3, lsl #3] + 11c: e0914003 adds r4, r1, r3 + 120: e59c3004 ldr r3, [ip, #4] + 124: e0835780 add r5, r3, r0, lsl #15 + 128: ee010ba0 vmla.f64 d0, d17, d16 + 12c: ec454b30 vmov d16, r4, r5 + 130: ee200b20 vmul.f64 d0, d0, d16 + 134: eeb70bc0 vcvt.f32.f64 s0, d0 + 138: e28dd008 add sp, sp, #8 + 13c: e8bd0030 pop {r4, r5} + 140: e12fff1e bx lr + 144: e1530000 cmp r3, r0 + 148: 2a00003d bcs 244 + 14c: e1a0308c lsl r3, ip, #1 + 150: e2433001 sub r3, r3, #1 + 154: e1530000 cmp r3, r0 + 158: 2a000030 bcs 220 + 15c: e35c0000 cmp ip, #0 + 160: a3a00000 movge r0, #0 + 164: ba000016 blt 1c4 + 168: e35c0502 cmp ip, #8388608 ; 0x800000 + 16c: 3ddf7a5d vldrcc s15, [pc, #372] ; 2e8 + 170: 3e200a27 vmulcc.f32 s0, s0, s15 + 174: 3e103a10 vmovcc r3, s0 + 178: 33c33102 biccc r3, r3, #-2147483648 ; 0x80000000 + 17c: 3243c52e subcc ip, r3, #192937984 ; 0xb800000 + 180: eaffffab b 34 + 184: eddf0b53 vldr d16, [pc, #332] ; 2d8 + 188: eeb47be0 vcmpe.f64 d7, d16 + 18c: eef1fa10 vmrs APSR_nzcv, fpscr + 190: ca00001f bgt 214 + 194: eddf0b51 vldr d16, [pc, #324] ; 2e0 + 198: eeb47be0 vcmpe.f64 d7, d16 + 19c: eef1fa10 vmrs APSR_nzcv, fpscr + 1a0: 8affffca bhi d0 + 1a4: e28dd008 add sp, sp, #8 + 1a8: e8bd0030 pop {r4, r5} + 1ac: eafffffe b 0 + 1ac: R_ARM_JUMP24 __math_uflowf + 1b0: e35c05fe cmp ip, #1065353216 ; 0x3f800000 + 1b4: 13510000 cmpne r1, #0 + 1b8: 1a000038 bne 2a0 + 1bc: eeb70a00 vmov.f32 s0, #112 ; 0x3f800000 1.0 + 1c0: eaffffdc b 138 + 1c4: e7e73bd2 ubfx r3, r2, #23, #8 + 1c8: e353007e cmp r3, #126 ; 0x7e + 1cc: 9a00000d bls 208 + 1d0: e3530096 cmp r3, #150 ; 0x96 + 1d4: 8a000022 bhi 264 + 1d8: e3a01001 mov r1, #1 + 1dc: e2633096 rsb r3, r3, #150 ; 0x96 + 1e0: e1a03311 lsl r3, r1, r3 + 1e4: e2431001 sub r1, r3, #1 + 1e8: e1110002 tst r1, r2 + 1ec: 1a000005 bne 208 + 1f0: e1130002 tst r3, r2 + 1f4: 13a00001 movne r0, #1 + 1f8: 03a00000 moveq r0, #0 + 1fc: e1a00800 lsl r0, r0, #16 + 200: e3ccc102 bic ip, ip, #-2147483648 ; 0x80000000 + 204: eaffffd7 b 168 + 208: e28dd008 add sp, sp, #8 + 20c: e8bd0030 pop {r4, r5} + 210: eafffffe b 0 + 210: R_ARM_JUMP24 __math_invalidf + 214: e28dd008 add sp, sp, #8 + 218: e8bd0030 pop {r4, r5} + 21c: eafffffe b 0 + 21c: R_ARM_JUMP24 __math_oflowf + 220: ee200a00 vmul.f32 s0, s0, s0 + 224: e35c0000 cmp ip, #0 + 228: ba00000f blt 26c + 22c: e3520000 cmp r2, #0 + 230: beb77a00 vmovlt.f32 s14, #112 ; 0x3f800000 1.0 + 234: bec77a00 vdivlt.f32 s15, s14, s0 + 238: bdcd7a01 vstrlt s15, [sp, #4] + 23c: bd9d0a01 vldrlt s0, [sp, #4] + 240: eaffffbc b 138 + 244: e3510000 cmp r1, #0 + 248: 0affffdb beq 1bc + 24c: e1a0308c lsl r3, ip, #1 + 250: e35304ff cmp r3, #-16777216 ; 0xff000000 + 254: 935104ff cmpls r1, #-16777216 ; 0xff000000 + 258: 0a00001b beq 2cc + 25c: ee300a20 vadd.f32 s0, s0, s1 + 260: eaffffb4 b 138 + 264: e3a00000 mov r0, #0 + 268: eaffffe4 b 200 + 26c: e7e73bd2 ubfx r3, r2, #23, #8 + 270: e243107f sub r1, r3, #127 ; 0x7f + 274: e3510017 cmp r1, #23 + 278: 8affffeb bhi 22c + 27c: e3a01001 mov r1, #1 + 280: e2633096 rsb r3, r3, #150 ; 0x96 + 284: e1a03311 lsl r3, r1, r3 + 288: e2431001 sub r1, r3, #1 + 28c: e1110002 tst r1, r2 + 290: 1affffe5 bne 22c + 294: e1130002 tst r3, r2 + 298: 1eb10a40 vnegne.f32 s0, s0 + 29c: eaffffe2 b 22c + 2a0: e35104ff cmp r1, #-16777216 ; 0xff000000 + 2a4: 01a0308c lsleq r3, ip, #1 + 2a8: 1affffeb bne 25c + 2ac: e353047f cmp r3, #2130706432 ; 0x7f000000 + 2b0: e1e02002 mvn r2, r2 + 2b4: 33a03000 movcc r3, #0 + 2b8: 23a03001 movcs r3, #1 + 2bc: e1530fa2 cmp r3, r2, lsr #31 + 2c0: 0e200aa0 vmuleq.f32 s0, s1, s1 + 2c4: 1d9f0a08 vldrne s0, [pc, #32] ; 2ec + 2c8: eaffff9a b 138 + 2cc: e353047f cmp r3, #2130706432 ; 0x7f000000 + 2d0: 1afffff5 bne 2ac + 2d4: eaffffb8 b 1bc + 2d8: ffd1d571 .word 0xffd1d571 + 2dc: 405fffff .word 0x405fffff + 2e0: 00000000 .word 0x00000000 + 2e4: c062c000 .word 0xc062c000 + 2e8: 4b000000 .word 0x4b000000 + 2ec: 00000000 .word 0x00000000 + +Disassembly of section .text.scalbn: + +00000000 : + 0: e3500b01 cmp r0, #1024 ; 0x400 + 4: ba000010 blt 4c + 8: eddf0b26 vldr d16, [pc, #152] ; a8 + c: e30037fe movw r3, #2046 ; 0x7fe + 10: e1500003 cmp r0, r3 + 14: ee200b20 vmul.f64 d0, d0, d16 + 18: da000006 ble 38 + 1c: e2403e7f sub r3, r0, #2032 ; 0x7f0 + 20: ee200b20 vmul.f64 d0, d0, d16 + 24: e243300e sub r3, r3, #14 + 28: e30003ff movw r0, #1023 ; 0x3ff + 2c: e1530000 cmp r3, r0 + 30: d0800003 addle r0, r0, r3 + 34: c0800000 addgt r0, r0, r0 + 38: e3a02000 mov r2, #0 + 3c: e1a03a00 lsl r3, r0, #20 + 40: ec432b30 vmov d16, r2, r3 + 44: ee200b20 vmul.f64 d0, d0, d16 + 48: e12fff1e bx lr + 4c: e30f3c02 movw r3, #64514 ; 0xfc02 + 50: e34f3fff movt r3, #65535 ; 0xffff + 54: e1500003 cmp r0, r3 + 58: a2800fff addge r0, r0, #1020 ; 0x3fc + 5c: a2800003 addge r0, r0, #3 + 60: aafffff4 bge 38 + 64: e2802ff2 add r2, r0, #968 ; 0x3c8 + 68: eddf0b10 vldr d16, [pc, #64] ; b0 + 6c: e2822001 add r2, r2, #1 + 70: e1520003 cmp r2, r3 + 74: a2800d1f addge r0, r0, #1984 ; 0x7c0 + 78: ee200b20 vmul.f64 d0, d0, d16 + 7c: a2800008 addge r0, r0, #8 + 80: aaffffec bge 38 + 84: e2802e79 add r2, r0, #1936 ; 0x790 + 88: ee200b20 vmul.f64 d0, d0, d16 + 8c: e2822002 add r2, r2, #2 + 90: e30003ff movw r0, #1023 ; 0x3ff + 94: e1520003 cmp r2, r3 + 98: a0800002 addge r0, r0, r2 + 9c: b0800003 addlt r0, r0, r3 + a0: eaffffe4 b 38 + a4: e320f000 nop {0} + a8: 00000000 .word 0x00000000 + ac: 7fe00000 .word 0x7fe00000 + b0: 00000000 .word 0x00000000 + b4: 03600000 .word 0x03600000 + +Disassembly of section .text.sinf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e3001fda movw r1, #4058 ; 0xfda + c: e3431f49 movt r1, #16201 ; 0x3f49 + 10: e24dd00c sub sp, sp, #12 + 14: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 18: e1530001 cmp r3, r1 + 1c: 8a00000c bhi 54 + 20: e35305e6 cmp r3, #964689920 ; 0x39800000 + 24: 2a000029 bcs d0 + 28: e3a03000 mov r3, #0 + 2c: e3473f80 movt r3, #32640 ; 0x7f80 + 30: e0033002 and r3, r3, r2 + 34: e3530000 cmp r3, #0 + 38: 0d9f7a5a vldreq s14, [pc, #360] ; 1a8 + 3c: 1d9f7a5a vldrne s14, [pc, #360] ; 1ac + 40: 0e207a07 vmuleq.f32 s14, s0, s14 + 44: 1e307a07 vaddne.f32 s14, s0, s14 + 48: ed8d7a00 vstr s14, [sp] + 4c: e28dd00c add sp, sp, #12 + 50: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 54: e30513d1 movw r1, #21457 ; 0x53d1 + 58: e344107b movt r1, #16507 ; 0x407b + 5c: e1a02fa2 lsr r2, r2, #31 + 60: e1530001 cmp r3, r1 + 64: 8a00000b bhi 98 + 68: e30c1be3 movw r1, #52195 ; 0xcbe3 + 6c: e3441016 movt r1, #16406 ; 0x4016 + 70: eeb70ac0 vcvt.f64.f32 d0, s0 + 74: e1530001 cmp r3, r1 + 78: 8a00002a bhi 128 + 7c: eddf0b41 vldr d16, [pc, #260] ; 188 + 80: e3520000 cmp r2, #0 + 84: 0a00002d beq 140 + 88: ee300b20 vadd.f64 d0, d0, d16 + 8c: ebfffffe bl 0 + 8c: R_ARM_CALL __cosdf + 90: eeb10a40 vneg.f32 s0, s0 + 94: eaffffec b 4c + 98: e30311d5 movw r1, #12757 ; 0x31d5 + 9c: e34410e2 movt r1, #16610 ; 0x40e2 + a0: e1530001 cmp r3, r1 + a4: 8a00000d bhi e0 + a8: e30e1ddf movw r1, #60895 ; 0xeddf + ac: e34410af movt r1, #16559 ; 0x40af + b0: eeb70ac0 vcvt.f64.f32 d0, s0 + b4: e1530001 cmp r3, r1 + b8: 8a00002a bhi 168 + bc: eddf0b33 vldr d16, [pc, #204] ; 190 + c0: e3520000 cmp r2, #0 + c4: 0a000021 beq 150 + c8: ee300b20 vadd.f64 d0, d0, d16 + cc: ea00001c b 144 + d0: eeb70ac0 vcvt.f64.f32 d0, s0 + d4: e28dd00c add sp, sp, #12 + d8: e49de004 pop {lr} ; (ldr lr, [sp], #4) + dc: eafffffe b 0 + dc: R_ARM_JUMP24 __sindf + e0: e30f2fff movw r2, #65535 ; 0xffff + e4: e3472f7f movt r2, #32639 ; 0x7f7f + e8: e1530002 cmp r3, r2 + ec: 8e300a40 vsubhi.f32 s0, s0, s0 + f0: 8affffd5 bhi 4c + f4: e1a0000d mov r0, sp + f8: ebfffffe bl 0 + f8: R_ARM_CALL __rem_pio2f + fc: e2000003 and r0, r0, #3 + 100: ed9d0b00 vldr d0, [sp] + 104: e3500001 cmp r0, #1 + 108: 0a000014 beq 160 + 10c: e3500002 cmp r0, #2 + 110: 0a000019 beq 17c + 114: e3500000 cmp r0, #0 + 118: 0a000018 beq 180 + 11c: ebfffffe bl 0 + 11c: R_ARM_CALL __cosdf + 120: eeb10a40 vneg.f32 s0, s0 + 124: eaffffc8 b 4c + 128: eddf0b1a vldr d16, [pc, #104] ; 198 + 12c: e3520000 cmp r2, #0 + 130: 1e300b20 vaddne.f64 d0, d0, d16 + 134: 0e300b60 vsubeq.f64 d0, d0, d16 + 138: eeb10b40 vneg.f64 d0, d0 + 13c: eaffffe4 b d4 + 140: ee300b60 vsub.f64 d0, d0, d16 + 144: e28dd00c add sp, sp, #12 + 148: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 14c: eafffffe b 0 + 14c: R_ARM_JUMP24 __cosdf + 150: ee300b60 vsub.f64 d0, d0, d16 + 154: ebfffffe bl 0 + 154: R_ARM_CALL __cosdf + 158: eeb10a40 vneg.f32 s0, s0 + 15c: eaffffba b 4c + 160: ebfffffe bl 0 + 160: R_ARM_CALL __cosdf + 164: eaffffb8 b 4c + 168: eddf0b0c vldr d16, [pc, #48] ; 1a0 + 16c: e3520000 cmp r2, #0 + 170: 1e300b20 vaddne.f64 d0, d0, d16 + 174: 0e300b60 vsubeq.f64 d0, d0, d16 + 178: eaffffd5 b d4 + 17c: eeb10b40 vneg.f64 d0, d0 + 180: ebfffffe bl 0 + 180: R_ARM_CALL __sindf + 184: eaffffb0 b 4c + 188: 54442d18 .word 0x54442d18 + 18c: 3ff921fb .word 0x3ff921fb + 190: 7f3321d2 .word 0x7f3321d2 + 194: 4012d97c .word 0x4012d97c + 198: 54442d18 .word 0x54442d18 + 19c: 400921fb .word 0x400921fb + 1a0: 54442d18 .word 0x54442d18 + 1a4: 401921fb .word 0x401921fb + 1a8: 03800000 .word 0x03800000 + 1ac: 7b800000 .word 0x7b800000 + +Disassembly of section .text.sqrt: + +00000000 : + 0: eeb10bc0 vsqrt.f64 d0, d0 + 4: e12fff1e bx lr + +Disassembly of section .text.sqrtf: + +00000000 : + 0: eeb10ac0 vsqrt.f32 s0, s0 + 4: e12fff1e bx lr + +Disassembly of section .text.tanf: + +00000000 : + 0: ee102a10 vmov r2, s0 + 4: e52de004 push {lr} ; (str lr, [sp, #-4]!) + 8: e3001fda movw r1, #4058 ; 0xfda + c: e3431f49 movt r1, #16201 ; 0x3f49 + 10: e24dd00c sub sp, sp, #12 + 14: e3c23102 bic r3, r2, #-2147483648 ; 0x80000000 + 18: e1530001 cmp r3, r1 + 1c: 8a00000c bhi 54 + 20: e35305e6 cmp r3, #964689920 ; 0x39800000 + 24: 2a00002a bcs d4 + 28: e3a03000 mov r3, #0 + 2c: e3473f80 movt r3, #32640 ; 0x7f80 + 30: e0033002 and r3, r3, r2 + 34: e3530000 cmp r3, #0 + 38: 0d9f7a48 vldreq s14, [pc, #288] ; 160 + 3c: 1d9f7a48 vldrne s14, [pc, #288] ; 164 + 40: 0e207a07 vmuleq.f32 s14, s0, s14 + 44: 1e307a07 vaddne.f32 s14, s0, s14 + 48: ed8d7a00 vstr s14, [sp] + 4c: e28dd00c add sp, sp, #12 + 50: e49df004 pop {pc} ; (ldr pc, [sp], #4) + 54: e30513d1 movw r1, #21457 ; 0x53d1 + 58: e344107b movt r1, #16507 ; 0x407b + 5c: e1a02fa2 lsr r2, r2, #31 + 60: e1530001 cmp r3, r1 + 64: 8a00000c bhi 9c + 68: e30c1be3 movw r1, #52195 ; 0xcbe3 + 6c: e3441016 movt r1, #16406 ; 0x4016 + 70: eeb70ac0 vcvt.f64.f32 d0, s0 + 74: e1530001 cmp r3, r1 + 78: 8a00001a bhi e8 + 7c: eddf0b2f vldr d16, [pc, #188] ; 140 + 80: e3520000 cmp r2, #0 + 84: 0a000010 beq cc + 88: ee300b20 vadd.f64 d0, d0, d16 + 8c: e3a00001 mov r0, #1 + 90: e28dd00c add sp, sp, #12 + 94: e49de004 pop {lr} ; (ldr lr, [sp], #4) + 98: eafffffe b 0 + 98: R_ARM_JUMP24 __tandf + 9c: e30311d5 movw r1, #12757 ; 0x31d5 + a0: e34410e2 movt r1, #16610 ; 0x40e2 + a4: e1530001 cmp r3, r1 + a8: 8a000013 bhi fc + ac: e30e1ddf movw r1, #60895 ; 0xeddf + b0: e34410af movt r1, #16559 ; 0x40af + b4: eeb70ac0 vcvt.f64.f32 d0, s0 + b8: e1530001 cmp r3, r1 + bc: 8a000019 bhi 128 + c0: eddf0b20 vldr d16, [pc, #128] ; 148 + c4: e3520000 cmp r2, #0 + c8: 1affffee bne 88 + cc: ee300b60 vsub.f64 d0, d0, d16 + d0: eaffffed b 8c + d4: eeb70ac0 vcvt.f64.f32 d0, s0 + d8: e3a00000 mov r0, #0 + dc: e28dd00c add sp, sp, #12 + e0: e49de004 pop {lr} ; (ldr lr, [sp], #4) + e4: eafffffe b 0 + e4: R_ARM_JUMP24 __tandf + e8: eddf0b18 vldr d16, [pc, #96] ; 150 + ec: e3520000 cmp r2, #0 + f0: 0a00000f beq 134 + f4: ee300b20 vadd.f64 d0, d0, d16 + f8: eafffff6 b d8 + fc: e30f2fff movw r2, #65535 ; 0xffff + 100: e3472f7f movt r2, #32639 ; 0x7f7f + 104: e1530002 cmp r3, r2 + 108: 8e300a40 vsubhi.f32 s0, s0, s0 + 10c: 8affffce bhi 4c + 110: e1a0000d mov r0, sp + 114: ebfffffe bl 0 + 114: R_ARM_CALL __rem_pio2f + 118: ed9d0b00 vldr d0, [sp] + 11c: e2000001 and r0, r0, #1 + 120: ebfffffe bl 0 + 120: R_ARM_CALL __tandf + 124: eaffffc8 b 4c + 128: eddf0b0a vldr d16, [pc, #40] ; 158 + 12c: e3520000 cmp r2, #0 + 130: 1affffef bne f4 + 134: ee300b60 vsub.f64 d0, d0, d16 + 138: eaffffe6 b d8 + 13c: e320f000 nop {0} + 140: 54442d18 .word 0x54442d18 + 144: 3ff921fb .word 0x3ff921fb + 148: 7f3321d2 .word 0x7f3321d2 + 14c: 4012d97c .word 0x4012d97c + 150: 54442d18 .word 0x54442d18 + 154: 400921fb .word 0x400921fb + 158: 54442d18 .word 0x54442d18 + 15c: 401921fb .word 0x401921fb + 160: 03800000 .word 0x03800000 + 164: 7b800000 .word 0x7b800000 diff --git a/tests/test_thumb_addend.py b/tests/test_thumb_addend.py new file mode 100644 index 0000000..99edd36 --- /dev/null +++ b/tests/test_thumb_addend.py @@ -0,0 +1,65 @@ +import pelfy._main as _main +import os + +def test_thumb_addend_extraction(): + # Path to the test object file + obj_path = os.path.join('tests', 'obj', 'stencils_armv7thumb_O3_THM_MOVW.o') + elf = _main.open_elf_file(obj_path) + + # Collect all relocations of interest + reloc_addends: list[tuple[str, int, int, str]] = [] + for reloc in elf.get_relocations(): + if reloc.type.startswith('R_ARM_THM'): + reloc_addends.append((reloc.type, reloc['r_offset'], reloc['r_addend'], reloc.symbol.name)) + + # Reference values from the .asm file (addend = 0 for all Thumb relocations) + reference = [ + ('R_ARM_THM_MOVW_ABS_NC', None, 0, 'dummy_int'), + ('R_ARM_THM_MOVT_ABS', None, 0, 'dummy_int'), + ('R_ARM_THM_MOVW_ABS_NC', None, 0, 'dummy_float'), + ('R_ARM_THM_MOVT_ABS', None, 0, 'dummy_float'), + ('R_ARM_THM_JUMP24', 0x14, 0, 'auxsub_get_42'), + ('R_ARM_THM_CALL', 0xA, 0, 'result_int'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float_int'), + ('R_ARM_THM_JUMP24', 0xC, 0, 'result_float_float'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_int_int'), + ('R_ARM_THM_JUMP24', 0xC, 0, 'result_int_float'), + ('R_ARM_THM_CALL', 0xA, 0, 'aux_get_42'), + ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2, 0, 'aux_get_42'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), + ('R_ARM_THM_JUMP24', 0x2, 0, 'result_int'), + ('R_ARM_THM_JUMP24', 0x4, 0, 'result_float'), + ('R_ARM_THM_JUMP24', 0x28, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2C, 0, 'sqrtf'), + ('R_ARM_THM_JUMP24', 0x20, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x24, 0, 'sqrtf'), + ('R_ARM_THM_CALL', 0xA, 0, 'expf'), + ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2, 0, 'expf'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), + ('R_ARM_THM_CALL', 0xA, 0, 'logf'), + ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2, 0, 'logf'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), + ('R_ARM_THM_CALL', 0xA, 0, 'sinf'), + ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2, 0, 'sinf'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), + ('R_ARM_THM_CALL', 0xA, 0, 'cosf'), + ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2, 0, 'cosf'), + ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), + ('R_ARM_THM_CALL', 0xA, 0, 'tanf'), + ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), + ('R_ARM_THM_CALL', 0x2, 0, 'tanf'), + ] + # For each reference, check that at least one matching relocation has the expected addend + for ref_type, _, ref_addend, ref_symbol in reference: + found = False + addend = 0 + for typ, offset, addend, symbol in reloc_addends: + if typ == ref_type and symbol == ref_symbol and addend == ref_addend: + found = True + break + assert found, f"Missing or incorrect addend for {ref_type} {ref_symbol} (value={addend:X}, expected {ref_addend})" From 5a77c7206429737c2b4b6c6574565cc1781afb0e Mon Sep 17 00:00:00 2001 From: Nicolas Date: Sat, 28 Feb 2026 20:57:43 +0100 Subject: [PATCH 13/15] EM_ARM data updated from ARM reference manual --- src/pelfy/_fields_data.py | 59 +++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 34 deletions(-) diff --git a/src/pelfy/_fields_data.py b/src/pelfy/_fields_data.py index 498f29d..c1fac05 100644 --- a/src/pelfy/_fields_data.py +++ b/src/pelfy/_fields_data.py @@ -390,50 +390,41 @@ relocation_table_types = { }, "EM_ARM": { 0: ("R_ARM_NONE", 0, ""), - - 1: ("R_ARM_PC24", 24, "S - P + A"), - 2: ("R_ARM_ABS32", 32, "S + A"), - 3: ("R_ARM_REL32", 32, "S - P + A"), - 4: ("R_ARM_LDR_PC_G0", 12, "S - P + A"), - + 1: ("R_ARM_PC24", 24, "((S + A) | T) - P"), + 2: ("R_ARM_ABS32", 32, "(S + A) | T"), + 3: ("R_ARM_REL32", 32, "((S + A) | T) - P"), + 4: ("R_ARM_LDR_PC_G0", 12, "S + A - P"), 5: ("R_ARM_ABS16", 16, "S + A"), 6: ("R_ARM_ABS12", 12, "S + A"), 7: ("R_ARM_THM_ABS5", 5, "S + A"), 8: ("R_ARM_ABS8", 8, "S + A"), - 9: ("R_ARM_SBREL32", 32, "S - B + A"), - - 10: ("R_ARM_THM_CALL", 22, "S - P + A"), - 11: ("R_ARM_THM_PC8", 8, "S - P + A"), - 12: ("R_ARM_BREL_ADJ", 0, ""), + 9: ("R_ARM_SBREL32", 32, "((S + A) | T) - B(S)"), + 10: ("R_ARM_THM_CALL", 22, "((S + A) | T) - P"), + 11: ("R_ARM_THM_PC8", 8, "S + A - Pa"), + 12: ("R_ARM_BREL_ADJ", 0, "ChangeIn[B(S)] + A"), 13: ("R_ARM_TLS_DESC", 0, ""), 14: ("R_ARM_THM_SWI8", 8, "S + A"), - 15: ("R_ARM_XPC25", 25, ""), 16: ("R_ARM_THM_XPC22", 22, ""), - - 28: ("R_ARM_CALL", 24, "((S + A) - P) >> 2"), - 29: ("R_ARM_JUMP24", 24, "((S + A) - P) >> 2"), - 30: ("R_ARM_THM_JUMP24", 24, "((S + A) - P) >> 1"), - - 32: ("R_ARM_ALU_PCREL_7_0", 8, "(S - P + A) & 0x000000FF"), - 33: ("R_ARM_ALU_PCREL_15_8", 8, "(S - P + A) & 0x0000FF00"), - 34: ("R_ARM_ALU_PCREL_23_15", 9, "(S - P + A) & 0x00FF8000"), - - 35: ("R_ARM_LDR_SBREL_11_0", 12, "(S - B + A) & 0x00000FFF"), - 36: ("R_ARM_ALU_SBREL_19_12", 8, "(S - B + A) & 0x000FF000"), - 37: ("R_ARM_ALU_SBREL_27_20", 8, "(S - B + A) & 0x0FF00000"), - - 38: ("R_ARM_TARGET1", 32, "implementation defined"), - 39: ("R_ARM_SBREL31", 31, "S - B + A"), - + 17: ("R_ARM_TLS_DTPMOD32", 0, "Module[S]"), + 18: ("R_ARM_TLS_DTPOFF32", 0, "S + A - TLS"), + 19: ("R_ARM_TLS_TPOFF32", 0, "S + A - tp"), + 20: ("R_ARM_COPY", 0, ""), + 21: ("R_ARM_GLOB_DAT", 0, "(S + A) | T"), + 22: ("R_ARM_JUMP_SLOT", 0, "(S + A) | T"), + 23: ("R_ARM_RELATIVE", 0, "B(S) + A"), + 24: ("R_ARM_GOTOFF32", 0, "((S + A) | T) - GOT_ORG"), + 25: ("R_ARM_BASE_PREL", 0, "B(S) + A - P"), + 26: ("R_ARM_GOT_BREL", 0, "GOT(S) + A - GOT_ORG"), + 27: ("R_ARM_PLT32", 0, "((S + A) | T) - P"), + 28: ("R_ARM_CALL", 24, "((S + A) | T) - P"), + 29: ("R_ARM_JUMP24", 24, "((S + A) | T) - P"), + 30: ("R_ARM_THM_JUMP24", 24, "((S + A) | T) - P"), 40: ("R_ARM_V4BX", 0, ""), - 41: ("R_ARM_TARGET2", 32, "implementation defined"), - 42: ("R_ARM_PREL31", 31, "S - P + A"), - - 43: ("R_ARM_MOVW_ABS_NC", 16, "S + A"), + 42: ("R_ARM_PREL31", 31, "((S + A) | T) - P"), + 43: ("R_ARM_MOVW_ABS_NC", 16, "(S + A) | T"), 44: ("R_ARM_MOVT_ABS", 16, "S + A"), - - 47: ("R_ARM_THM_MOVW_ABS_NC", 16, "S + A"), + 47: ("R_ARM_THM_MOVW_ABS_NC", 16, "(S + A) | T"), 48: ("R_ARM_THM_MOVT_ABS", 16, "S + A"), }, "EM_AARCH64": { From a8139e373947344cab181a142f1069104904fad7 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Sat, 28 Feb 2026 21:21:06 +0100 Subject: [PATCH 14/15] addend calculation for R_ARM_THM_PC22, R_ARM_THM_JUMP24 and R_ARM_THM_CALL fixed --- src/pelfy/_main.py | 79 +++++++++++++++----------------------- tests/test_arm_addend.py | 7 +--- tests/test_thumb_addend.py | 75 ++++++++++++++++++------------------ 3 files changed, 72 insertions(+), 89 deletions(-) diff --git a/src/pelfy/_main.py b/src/pelfy/_main.py index e7db9a7..98e106d 100644 --- a/src/pelfy/_main.py +++ b/src/pelfy/_main.py @@ -27,51 +27,12 @@ def open_elf_file(file_path: str) -> 'elf_file': return elf_file(f.read()) -def _decode_thumb_branch_imm(field: int, bits: int) -> int: - """ - Decode Thumb-2 wide branch immediate. - bits: 22 (R_ARM_THM_PC22) or 24 (R_ARM_THM_JUMP24) - """ - - h1 = (field >> 16) & 0xFFFF - h2 = field & 0xFFFF - - S = (h1 >> 10) & 1 - imm10 = h1 & 0x03FF - J1 = (h2 >> 13) & 1 - J2 = (h2 >> 11) & 1 - imm11 = h2 & 0x07FF - - # Decode J1/J2 → I1/I2 - I1 = (~(J1 ^ S)) & 1 - I2 = (~(J2 ^ S)) & 1 - - if bits == 24: - imm = ( - (S << 23) | - (I1 << 22) | - (I2 << 21) | - (imm10 << 11) | - (imm11 << 0) - ) - sign_bit = 23 - else: - assert bits == 22 - imm = ( - (S << 21) | - (I1 << 20) | - (I2 << 19) | - (imm10 << 9) | - (imm11 << 0) - ) - sign_bit = 21 - - # Sign extend - if imm & (1 << sign_bit): - imm |= ~((1 << (sign_bit + 1)) - 1) - - # Thumb branch offsets are halfword aligned - return imm << 1 +def _sign_extend(value: int, bits: int) -> int: + """Sign-extend a value with given bit width to 32 bits.""" + sign_bit = 1 << (bits - 1) + if value & sign_bit: + return value - (1 << bits) + return value class elf_symbol(): @@ -592,9 +553,33 @@ class elf_file: imm24 |= ~0xFFFFFF return imm24 << 2 if name == 'R_ARM_THM_PC22': - return _decode_thumb_branch_imm(field, 22) + # BL Encoding T2 + h1 = field & 0xFFFF + h2 = (field >> 16) & 0xFFFF + s = (h1 >> 10) & 0x1 # Bit 10 of h1 + imm10H = h1 & 0x3FF # Bits 9..0 of h1 + j1 = (h2 >> 13) & 0x1 # Bit 13 of h2 + j2 = (h2 >> 11) & 0x1 # Bit 11 of h2 + imm10L = (h2 >> 1) & 0x3FF # Bits 10..1 of h2 + i1 = ~(j1 ^ s) & 0x1 + i2 = ~(j2 ^ s) & 0x1 + imm22 = (s << 21) | (i1 << 20) | (i2 << 19) | (imm10H << 9) | imm10L + imm32 = _sign_extend(imm22 << 1, 23) # Shift left by 1, then sign-extend 23 bits + return imm32 if name in ('R_ARM_THM_JUMP24', 'R_ARM_THM_CALL'): - return _decode_thumb_branch_imm(field, 24) + # B.W Encoding T4 + h1 = field & 0xFFFF + h2 = (field >> 16) & 0xFFFF + s = (h1 >> 10) & 0x1 # Bit 10 of h1 + imm10 = h1 & 0x3FF # Bits 9..0 of h1 + j1 = (h2 >> 13) & 0x1 # Bit 13 of h2 + j2 = (h2 >> 11) & 0x1 # Bit 11 of h2 + imm11 = h2 & 0x7FF # Bits 10..0 of h2 + i1 = ~(j1 ^ s) & 0x1 + i2 = ~(j2 ^ s) & 0x1 + imm24 = (s << 23) | (i1 << 22) | (i2 << 21) | (imm10 << 11) | imm11 + imm32 = _sign_extend(imm24 << 1, 25) # Shift left by 1, then sign-extend 25 bits + return imm32 if name == 'R_ARM_THM_MOVW_ABS_NC' or name == 'R_ARM_THM_MOVT_ABS': i = (field >> 10) & 1 imm4 = field & 0xF diff --git a/tests/test_arm_addend.py b/tests/test_arm_addend.py index 4365315..c77e986 100644 --- a/tests/test_arm_addend.py +++ b/tests/test_arm_addend.py @@ -1,7 +1,8 @@ import pelfy._main as _main import os -def test_arm_addend_extraction(): + +def test_arm_addend_extraction() -> None: # Path to the test object file obj_path = os.path.join('tests', 'obj', 'stencils_armv7_O3.o') elf = _main.open_elf_file(obj_path) @@ -59,7 +60,3 @@ def test_arm_addend_extraction(): found = True break assert found, f"Missing or incorrect addend for {ref_type} offset=0x{ref_offset:X} symbol={ref_symbol} (value={addend}, expected {ref_addend})" - - print(found, f"Missing or incorrect addend for {ref_type} offset=0x{ref_offset:X} symbol={ref_symbol} (value={addend}, expected {ref_addend})") - - assert False \ No newline at end of file diff --git a/tests/test_thumb_addend.py b/tests/test_thumb_addend.py index 99edd36..a31f276 100644 --- a/tests/test_thumb_addend.py +++ b/tests/test_thumb_addend.py @@ -1,7 +1,8 @@ import pelfy._main as _main import os -def test_thumb_addend_extraction(): + +def test_thumb_addend_extraction() -> None: # Path to the test object file obj_path = os.path.join('tests', 'obj', 'stencils_armv7thumb_O3_THM_MOVW.o') elf = _main.open_elf_file(obj_path) @@ -13,46 +14,46 @@ def test_thumb_addend_extraction(): reloc_addends.append((reloc.type, reloc['r_offset'], reloc['r_addend'], reloc.symbol.name)) # Reference values from the .asm file (addend = 0 for all Thumb relocations) - reference = [ + reference: list[tuple[str, int | None, int, str]] = [ ('R_ARM_THM_MOVW_ABS_NC', None, 0, 'dummy_int'), ('R_ARM_THM_MOVT_ABS', None, 0, 'dummy_int'), ('R_ARM_THM_MOVW_ABS_NC', None, 0, 'dummy_float'), ('R_ARM_THM_MOVT_ABS', None, 0, 'dummy_float'), - ('R_ARM_THM_JUMP24', 0x14, 0, 'auxsub_get_42'), - ('R_ARM_THM_CALL', 0xA, 0, 'result_int'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float_int'), - ('R_ARM_THM_JUMP24', 0xC, 0, 'result_float_float'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_int_int'), - ('R_ARM_THM_JUMP24', 0xC, 0, 'result_int_float'), - ('R_ARM_THM_CALL', 0xA, 0, 'aux_get_42'), - ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2, 0, 'aux_get_42'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), - ('R_ARM_THM_JUMP24', 0x2, 0, 'result_int'), - ('R_ARM_THM_JUMP24', 0x4, 0, 'result_float'), - ('R_ARM_THM_JUMP24', 0x28, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2C, 0, 'sqrtf'), - ('R_ARM_THM_JUMP24', 0x20, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x24, 0, 'sqrtf'), - ('R_ARM_THM_CALL', 0xA, 0, 'expf'), - ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2, 0, 'expf'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), - ('R_ARM_THM_CALL', 0xA, 0, 'logf'), - ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2, 0, 'logf'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), - ('R_ARM_THM_CALL', 0xA, 0, 'sinf'), - ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2, 0, 'sinf'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), - ('R_ARM_THM_CALL', 0xA, 0, 'cosf'), - ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2, 0, 'cosf'), - ('R_ARM_THM_JUMP24', 0xA, 0, 'result_float'), - ('R_ARM_THM_CALL', 0xA, 0, 'tanf'), - ('R_ARM_THM_JUMP24', 0x12, 0, 'result_float'), - ('R_ARM_THM_CALL', 0x2, 0, 'tanf'), + ('R_ARM_THM_JUMP24', 0x14, -4, 'auxsub_get_42'), + ('R_ARM_THM_CALL', 0xA, -4, 'result_int'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_float_int'), + ('R_ARM_THM_JUMP24', 0xC, -4, 'result_float_float'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_int_int'), + ('R_ARM_THM_JUMP24', 0xC, -4, 'result_int_float'), + ('R_ARM_THM_CALL', 0xA, -4, 'aux_get_42'), + ('R_ARM_THM_JUMP24', 0x12, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2, -4, 'aux_get_42'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_float'), + ('R_ARM_THM_JUMP24', 0x2, -4, 'result_int'), + ('R_ARM_THM_JUMP24', 0x4, -4, 'result_float'), + ('R_ARM_THM_JUMP24', 0x28, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2C, -4, 'sqrtf'), + ('R_ARM_THM_JUMP24', 0x20, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x24, -4, 'sqrtf'), + ('R_ARM_THM_CALL', 0xA, -4, 'expf'), + ('R_ARM_THM_JUMP24', 0x12, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2, -4, 'expf'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_float'), + ('R_ARM_THM_CALL', 0xA, -4, 'logf'), + ('R_ARM_THM_JUMP24', 0x12, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2, -4, 'logf'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_float'), + ('R_ARM_THM_CALL', 0xA, -4, 'sinf'), + ('R_ARM_THM_JUMP24', 0x12, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2, -4, 'sinf'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_float'), + ('R_ARM_THM_CALL', 0xA, -4, 'cosf'), + ('R_ARM_THM_JUMP24', 0x12, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2, -4, 'cosf'), + ('R_ARM_THM_JUMP24', 0xA, -4, 'result_float'), + ('R_ARM_THM_CALL', 0xA, -4, 'tanf'), + ('R_ARM_THM_JUMP24', 0x12, -4, 'result_float'), + ('R_ARM_THM_CALL', 0x2, -4, 'tanf'), ] # For each reference, check that at least one matching relocation has the expected addend for ref_type, _, ref_addend, ref_symbol in reference: From 2be97956abd091dc9503588808741b9b89abe802 Mon Sep 17 00:00:00 2001 From: Nicolas Date: Sat, 28 Feb 2026 21:24:10 +0100 Subject: [PATCH 15/15] Type hints fixed for backwards compatibility for python 3.9 --- tests/test_thumb_addend.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/test_thumb_addend.py b/tests/test_thumb_addend.py index a31f276..342cac7 100644 --- a/tests/test_thumb_addend.py +++ b/tests/test_thumb_addend.py @@ -1,5 +1,6 @@ import pelfy._main as _main import os +from typing import Union def test_thumb_addend_extraction() -> None: @@ -14,7 +15,7 @@ def test_thumb_addend_extraction() -> None: reloc_addends.append((reloc.type, reloc['r_offset'], reloc['r_addend'], reloc.symbol.name)) # Reference values from the .asm file (addend = 0 for all Thumb relocations) - reference: list[tuple[str, int | None, int, str]] = [ + reference: list[tuple[str, Union[int, None], int, str]] = [ ('R_ARM_THM_MOVW_ABS_NC', None, 0, 'dummy_int'), ('R_ARM_THM_MOVT_ABS', None, 0, 'dummy_int'), ('R_ARM_THM_MOVW_ABS_NC', None, 0, 'dummy_float'),